Dual Clock FIFO Pointer Synchronization via Intermediary Circuits
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Solution Overview
Problem
Dual clock FIFO circuits face metastability issues due to skew between parallel digital bits indicating pointers, leading to inaccurate indications of FIFO emptiness or fullness, which can result in data loss when high-frequency clocks are involved.
Innovation Solution
A dual clock FIFO circuit design incorporating two component FIFO circuits, where one synchronizes the write pointer with the read clock and the other synchronizes the read pointer with the write clock, using comparators to accurately indicate FIFO status without data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dual clock FIFO circuits are used to transfer data between different clock domains, then data transfer capability is improved, but metastability issues arise due to skew between parallel digital bits indicating pointers
Solution Approach 1:
The patent introduces intermediary FIFO circuits that act as mediators between the write and read clock domains. These intermediate FIFOs synchronize the write and read pointers by transferring them through the different clock domains, eliminating direct skew interactions and preventing metastability issues while maintaining data transfer capability between different clock frequencies
2Productivity
If high-frequency clocks are used to increase data transfer speed, then productivity is improved, but pointer skew errors increase leading to inaccurate FIFO status indication
Solution Approach 1:
The intermediary FIFO circuits serve as synchronization mediators that transfer pointers between high-frequency clock domains without direct skew. By routing pointers through intermediate storage elements clocked at different frequencies, the system maintains accurate FIFO status indication even when operating with high-frequency clocks that would otherwise cause significant pointer skew
3Device complexity
If pointers are synchronized directly between clock domains, then device complexity is reduced, but data loss occurs due to metastability
Solution Approach 1:
The patent segments the pointer synchronization process into multiple independent stages using separate FIFO circuits. Instead of a single direct synchronization path, the write pointer is synchronized through one FIFO and the read pointer through another, dividing the complex synchronization task into manageable segments that prevent metastability-induced data loss while maintaining reasonable system complexity
Data Source
AI summary
A first first-in first-out (FIFO) circuit includes a storage circuit, a second first-in first-out (FIFO) circuit, and a third first-in first-out (FIFO) circuit. The storage circuit stores write data at a write address in response to a write clock signal. The storage circuit outputs read data from a read address in response to a read clock signal. A write pointer indicating the write address is synchronized with the write clock signal. A read pointer indicating the read address is synchronized with the read clock signal. The second first-in first-out (FIFO) circuit synchronizes the write pointer with the read clock signal. The third first-in first-out (FIFO) circuit synchronizes the read pointer with the write clock signal.