Memory Controller Strobe Signal Delay Adjustment
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Solution Overview
Problem
Memory systems face challenges in increasing operating speeds due to varying sensitivities to process, voltage, and temperature variations, as well as changing operating conditions, leading to inconsistent memory performance across different memory types.
Innovation Solution
A memory controller is designed to provide timing strobe signals with adjustable delays to compensate for these variations, using a phase detector to compare return strobe signals with a clock signal and adjust delays for read and write operations, ensuring synchronized data transfer across multiple memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If operating speeds of memory systems are increased to improve performance, then productivity is improved, but reliability deteriorates due to varying sensitivities to process, voltage, and temperature variations
Solution Approach 1:
The patent implements dynamic timing adjustment by making the timing strobe signal delay variable rather than fixed. The memory controller continuously monitors return strobe signals from multiple memories and adjusts the delay of timing strobe signals in real-time to compensate for PVT variations, allowing the system to maintain reliable operation at high speeds by adapting to changing conditions.
Solution Approach 2:
The patent employs feedback mechanisms where the memory controller receives return strobe signals from each memory and uses phase detection to compare these signals. Based on the phase difference detected, the controller adjusts the timing strobe signal delays to ensure synchronized data transfer, creating a closed-loop control system that maintains reliability despite speed increases and environmental variations.
2Reliability
If timing is synchronized across multiple memories to improve reliability, then device complexity increases due to adjustable delays and phase detection mechanisms
Solution Approach 1:
The memory controller is designed with multi-functional components that perform multiple tasks. The phase detector not only compares return strobe signals but also generates control signals for timing adjustment. The timing strobe signal generator simultaneously manages multiple memories with different delays. This universal design reduces overall system complexity by consolidating functions into single components rather than requiring separate dedicated circuits for each function.
Solution Approach 2:
The patent adjusts timing parameters (delay values of timing strobe signals) rather than changing the fundamental architecture. By modifying controllable parameters like delay amounts and phase relationships, the system achieves synchronized data transfer across diverse memories without requiring complex structural modifications. This parameter-based approach simplifies the controller design compared to structural changes.
Data Source
AI summary
Apparatuses and methods for providing strobe signals to memories are described herein. An example apparatus may include a plurality of memories and a memory controller. The memory controller may be coupled to the plurality of memories and configured to receive an input clock signal. The memory controller may further be configured to provide a timing strobe signal having a delay relative to the input clock signal to a memory of the plurality of memories. The memory controller may further be configured to receive a return strobe signal from the plurality of memories. In some examples, the return strobe signal may be based at least in part on the timing strobe signal and the memory controller may be configured to adjust the delay based, at least in part, on a phase difference of the input clock signal and the return strobe signal.