SRAM Bitcell Reset via Biasing Circuit Power Collapse
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Solution Overview
Problem
Existing SRAM cache memory technologies face inefficiencies in resetting multiple valid bits to an invalid state, as individual resetting is time-consuming, and methods requiring specialized bitcells or increased drive strength in bitline drivers complicate manufacturing and increase memory density.
Innovation Solution
A biasing circuit is introduced to apply voltage or current bias to SRAM bitcells during reset operations, collapsing power to a lower level and then restoring it, allowing for a single reset operation without the need for specialized bitcells or increased drive strength in the reset circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If specialized SRAM bitcells with additional transistors are used for reset operations, then the ability to reset multiple valid bits in a single operation is improved, but the manufacturing complexity increases and memory density decreases
Solution Approach 1:
A biasing circuit is introduced as an intermediary component that applies voltage or current bias to SRAM bitcells during reset operations. This biasing circuit acts as a mediator between the power supply and the bitcells, enabling single-operation resetting without modifying the bitcell structure itself, thus avoiding increased manufacturing complexity while maintaining high productivity
Solution Approach 2:
The invention changes the power supply parameters by collapsing power to a lower level and then restoring it, while simultaneously applying voltage or current bias through the biasing circuit. This parameter change approach enables efficient reset operations without requiring additional transistors in the bitcells, thereby maintaining standard manufacturing processes and memory density
2Productivity
If the drive strength of bitline drivers is increased to force bitcell states, then the ability to reset multiple bitcells is improved, but the memory density increases
Solution Approach 1:
Instead of increasing drive strength, the invention changes the operational parameters by collapsing power to a lower level and applying voltage or current bias through the biasing circuit. This allows multiple bitcells to be reset without requiring larger or more numerous transistors in the bitline drivers, thereby maintaining memory density while achieving the desired reset capability
Solution Approach 2:
The reset operation employs periodic action through the sequence of collapsing power to a lower level, applying bias, and then restoring power. This time-dependent periodic approach enables efficient resetting of multiple bitcells without requiring sustained high drive strength, thus avoiding increased memory density
Data Source
AI summary
Circuits for voltage or current biasing static random access memory (SRAM) bitcells during SRAM reset operations are disclosed. Related systems and methods are also disclosed. To reset a plurality of SRAM bitcells in a single reset operation, a biasing circuit is provided and coupled to the plurality of SRAM bitcells. The biasing circuit is configured to apply a voltage or current bias to the SRAM bitcells during a reset operation after power provided to the SRAM bitcells is collapsed to a collapsed power level below an operational power level. The bias is applied as the power to the SRAM bitcells is restored to an operational power level, thus forcing the SRAM bitcells into a desired state. In this manner, the SRAM bitcells can be reset in a single reset operation without need for an increased drive strength from a reset circuit and without need to provide specialized SRAM bitcells.