Unified DRAM Column-Command Address Control Circuit
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Solution Overview
Problem
Conventional DDR SDRAM devices require separate register paths for read and write operations due to differing latencies, complicating column-command address control.
Innovation Solution
Integration of latency controls for read and write operations using a control unit and a FIFO register, where the control unit sets latency values to determine a period number, producing input and output pointers that are synchronized with a clock signal, allowing the FIFO register to store and output column-command addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate register paths are used for read and write operations, then the differing latencies can be controlled independently, but the circuit complexity increases
Solution Approach 1:
The patent merges separate read and write register paths into a unified address control structure. A single write-address register and latch unit serve both read and write operations by controlling when address signals are loaded and held, eliminating the need for completely separate paths while maintaining independent latency control through a unified latency counter that adjusts timing for different operation types.
Solution Approach 2:
The address control circuit is designed with multi-functionality where the same register and latch units handle both read and write column addresses. The write-address register and latch unit can operate in different modes (read or write) based on control signals, allowing one component to perform multiple functions that previously required separate dedicated circuits.
2Device complexity
If a unified address control structure is used, then the circuit complexity is reduced, but the ability to independently control read and write latencies is compromised
Solution Approach 1:
The unified address control structure employs dynamic timing adjustment through a latency counter that can be programmed with different values for read and write operations. The counter dynamically controls the timing of address signal propagation and latch enabling, allowing the same hardware to adapt its behavior to meet different latency requirements for reads versus writes without requiring separate static paths.
3Productivity
If separate register paths are used, then read and write operations can be optimized independently, but the overall device productivity decreases
Solution Approach 1:
By combining the address control functions into a unified structure with a single write-address register and latch unit, the patent reduces the total number of components and interconnections required. This merging eliminates redundant circuitry while maintaining the ability to handle both read and write operations efficiently, thereby improving overall device productivity by reducing resource overhead.
Data Source
AI summary
The present invention provides a circuit for controlling a column-command address corresponding to a specific column of a DRAM array. The circuit includes a control unit and a FIFO register. The control unit determines a period number, and synchronously produces an input pointer and an output pointer, wherein the output pointer is lagged behind the input pointer by the period number. The FIFO register utilizes the input pointer to store the column-command address, and utilizes the output pointer to output the column-command address.