Shift Register Memory With Layer Shifting And Wear Reduction
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Solution Overview
Problem
Current nonvolatile memory systems, such as solid state drives (SSDs) using magnetic domain wall shift memories, face challenges in efficient data storage and retrieval due to the destructive nature of read operations and the need for sequential shifting of data layers, which affects performance and endurance.
Innovation Solution
The implementation of a shift register memory system with a control circuit that manages data storage and retrieval by shifting layers along shift strings, using shift trimming to determine optimal shift parameters for each magnetic domain wall, allowing for parallel read/write operations and reducing wear on the memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential shifting of data layers is used for read operations, then data can be retrieved from shift register memory, but read operations become destructive and performance is degraded
Solution Approach 1:
The memory block is divided into multiple segments corresponding to different read depths. Each segment can be independently accessed by applying a specific number of shift pulses, allowing parallel read operations at different depths without interfering with each other, thus improving read performance while maintaining data integrity
Solution Approach 2:
Data is pre-positioned in the shift register memory during write operations with anticipated future read requirements. By preparing data at optimal positions in advance, the system eliminates the need for sequential shifting during read operations, thereby preventing performance degradation and avoiding destructive read issues
2Ease of operation
If sequential shifting operations are performed for each read/write operation, then data access is possible, but the memory endurance is reduced due to increased wear
Solution Approach 1:
The shift register memory is segmented into multiple independent data paths, each capable of handling read/write operations simultaneously. This segmentation distributes the wear across multiple paths rather than concentrating it in a single sequential path, thereby extending the overall memory lifespan while maintaining ease of data access
Solution Approach 2:
Multiple read and write operations are merged into a single parallel operation by simultaneously accessing different segments of the memory block. This combining of operations reduces the total number of shift cycles required, thereby reducing cumulative wear on the memory cells while preserving full data access capability
3Device complexity
If uniform shift parameters are used for all magnetic domain walls, then control circuit complexity is reduced, but shift register memory performance is suboptimal
Solution Approach 1:
The control circuit is designed to apply locally optimized shift parameters to different segments of the memory block based on their specific characteristics. Each segment can have tailored shift pulse widths, amplitudes, or frequencies optimized for its particular data retention and access patterns, thereby improving overall data access performance while the modular architecture prevents excessive complexity increase
Solution Approach 2:
The control circuit implements dynamic parameter adjustment where shift parameters are automatically adapted based on real-time feedback from the memory state. This dynamic optimization allows the system to maintain peak performance across varying operating conditions without requiring manually tuned uniform parameters, balancing complexity and performance through adaptive control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data access performance, extends the memory's lifespan by reducing wear, and improves operational efficiency through optimized shift parameter determination for each magnetic domain wall, enabling concurrent read and write operations.
Implementation Method 1
shift register type memories in which write and read of the data are carried out using the first-in first-out method or the last-in first-out (LIFO) method are being developed as next-generation nonvolatile memories
Data Source
AI summary
According to one embodiment, a shift register memory includes blocks and a control circuit. The blocks each includes data storing shift strings. Each of the data storing shift strings includes layers. The control circuit performs storing and reading data by shifting one layer of the layers, in a direction along each of the data storing shift strings. The reading includes reading data from a first layer of the layers. The storing includes storing data to a second layer of the layers. The control circuit reads first data stored in one or more third layers of the layers, the one or more third layers being successive from the first layer, determines a shift parameter in accordance with the reading of the first data, and performs the reading using the determined shift parameter.