Dynamic Wordline Assist Circuit for SRAM Stability and Writeability
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Solution Overview
Problem
The 6T SRAM cell faces challenges in achieving a balance between cell stability and writeability under conditions of low voltage operation, high process variation, and area efficiency, with existing techniques often resulting in tradeoffs that compromise either stability or writeability.
Innovation Solution
A wordline stability assist circuit is introduced, which activates during read or write cycles to limit the wordline supply and deactivates after a delay, enhancing stability and writeability by dynamically altering the wordline voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the wordline supply is limited to improve stability, then cell stability improves, but read/write performance deteriorates
Solution Approach 1:
The patent applies dynamics by making the wordline assist circuit configurable and time-dependent. The circuit can be dynamically enabled or disabled based on operational mode (read vs. write), and includes a delay mechanism that automatically disables the assist function after a predetermined time period during write operations. This dynamic behavior allows the system to optimize for stability during reads while maintaining performance during writes.
Solution Approach 2:
The patent changes the parameter of wordline voltage supply by introducing an assist circuit that can modify the wordline voltage characteristics. During read operations, the assist circuit is enabled to provide enhanced stability through modified voltage supply. During write operations, the assist circuit is disabled or automatically turns off after a delay, allowing full voltage supply for optimal write performance. This parameter change resolves the contradiction between stability and performance.
2Stability of the object's composition
If the wordline assist circuit is always activated to improve stability, then cell stability improves, but writeability deteriorates
Solution Approach 1:
The patent implements periodic action through a delay mechanism that automatically disables the wordline assist circuit after a predetermined time period following wordline activation during write operations. This periodic enabling and disabling ensures that the assist circuit provides stability only during the critical initial phase, then stops to allow full write capability. This resolves the contradiction by providing stability when needed while removing the constraint during the write operation.
Solution Approach 2:
The system transitions from a static always-on assist circuit to a dynamic circuit that changes state based on timing and operational mode. The delay mechanism creates a time-dependent behavior where the assist function is active initially then automatically deactivates, providing the necessary stability during setup while enabling full writeability during the actual write operation.
3Object-affected harmful factors
If voltage control is optimized for stability, then read disturb effects reduce, but write performance deteriorates
Solution Approach 1:
The patent changes the voltage control parameter dynamically based on operational mode. During read operations, the wordline assist circuit is enabled to provide optimized voltage control that reduces read disturb effects. During write operations, the assist circuit is disabled or automatically turns off after a delay, allowing unrestricted voltage supply for optimal write performance. This parameter change resolves the contradiction between reducing harmful read disturb effects and maintaining write performance.
Solution Approach 2:
The voltage control system becomes dynamic rather than static, with the assist circuit's voltage limiting function being enabled or disabled based on the operational phase. This dynamic voltage control allows the system to protect against read disturb during reads while providing full voltage headroom for writes, resolving the performance tradeoff.
Data Source
AI summary
A dynamic wordline assist circuit for improving performance of an SRAM. An SRAM is disclosed that includes a plurality of memory cells, wherein each memory cell is coupled to a wordline and a pair of bitlines; and a wordline assist circuit coupled to the wordline, wherein the wordline assist circuit includes a first input for activating the wordline assist circuit during a read or write cycle and includes a second input for deactivating the wordline assist circuit during the read or write cycle after a delay.