Acknowledgement Forwarding in Network Processor Pipelines

Solution Overview

Problem

Current data packet processing pipelines in telecommunications networks require a round trip acknowledgement for each resource access request, leading to increased latency and reduced throughput due to the need for acknowledgement latency to be a multiple of the number of data packets processed.

Innovation Solution

Implementing an acknowledgment forwarding process that allows a logical block to generate a resource request and send a unique identification to a subsequent block for processing, enabling non-blocking data packet processing by hiding transmission latency and reducing overall processing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a round trip acknowledgement is required for each resource access request in the pipeline, then data integrity is ensured, but processing latency increases and throughput decreases

Engineering Contradiction:

Improvedata integrityVSAvoidprocessing latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by forwarding the unique identification of the write request to the next logical block before the acknowledgement is received. This allows subsequent processing to begin in advance, hiding the acknowledgement latency and reducing overall processing time while maintaining data integrity through the use of the unique identification for tracking.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements continuity of useful action by enabling the pipeline to continue processing data packets without interruption. By forwarding the unique identification ahead of the acknowledgement, the pipeline maintains continuous flow of data through all logical blocks, preventing idle waiting periods and maximizing throughput.

Inventive Principle:

Principle #20Continuity of useful action

2Reliability

If a round trip acknowledgement is required for each resource access request, then data integrity is ensured, but pipeline throughput is reduced

Engineering Contradiction:

Improvedata integrityVSAvoidpipeline throughput

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by forwarding the unique identification of the write request to the next logical block before the acknowledgement is received. This allows subsequent processing to begin in advance, hiding the acknowledgement latency and reducing overall processing time while maintaining data integrity through the use of the unique identification for tracking.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements continuity of useful action by enabling the pipeline to continue processing data packets without interruption. By forwarding the unique identification ahead of the acknowledgement, the pipeline maintains continuous flow of data through all logical blocks, preventing idle waiting periods and maximizing throughput.

Inventive Principle:

Principle #20Continuity of useful action

3Stability of the object's composition

If acknowledgement latency must be a multiple of the number of data packets processed, then proper sequencing is maintained, but processing efficiency decreases

Engineering Contradiction:

Improvepacket sequencingVSAvoidprocessing efficiency

Core Design Contradiction:

Stability of the object's compositionVSProductivity

Solution Approach 1:

The patent uses copying by creating and forwarding a copy of the unique identification of the write request to the next logical block. This copy allows the pipeline to track and manage multiple data packets independently, maintaining proper sequencing without requiring the processing efficiency to be limited by acknowledgement latency multiples.

Inventive Principle:

Principle #26Copying

Data Source

PatentUS9317289B2Acknowledgement forwarding

Publication Date: 2016.04.19 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)

AI summary

A method for processing data packets in a pipeline and executed by a network processor. The pipeline includes a plurality of logical blocks, each logical block configured to process one stage of the pipeline. Each data packet includes a descriptor and a data. The network processor is coupled to a resource for storing the data. The method reduces latency and enables non-blocking processing of data packets by forwarding a unique identification of a write request from a first logical block to a subsequent second logical block in the pipeline, the write request to modify the data in the resource. The method includes receiving the descriptor for processing at the first logical block, generating the write request and the unique identification for the write request, transmitting the write request to the resource, and transmitting the unique identification towards the second logical block before an acknowledgement is returned by the resource.