Concurrent Instruction Execution TRIZ Cases
- Dynamic Scheduling for Low-Latency SIMD Data Processing
Parallel distributed scheduler dynamically assigns tasks to reduce processing latency on SIMD devices.
- Load-Hit-Store Hazard Prediction in Out-of-Order Processor Cores
A processor core uses a load-hit-store detection table to tag instructions at dispatch.
- Dual Controller Image Processing System for Cost Reduction
Segmenting controllers separates high-speed image processing from general control tasks, reducing component costs while maintaining recording efficiency.
- Store-Forwarding via Effective Address Detection in Out-of-Order Processors
An effective address directory and translation table detect load-hit-store hazards without real addresses, reducing chip area and power consumption.
- Workflow Manager for 5G Media Processing Functions
Orchestrating distributed media processing functions via a workflow manager resolves complexity and compatibility contradictions in 5G systems.