Store-Forwarding via Effective Address Detection in Out-of-Order Processors

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Solution Overview

Problem

Out-of-order processors face challenges in efficiently executing load and store instructions due to hazards like load-hit-store (LHS) situations, where younger load instructions may execute ahead of older store instructions, leading to incorrect results and pipeline flushes, and existing solutions require real addresses for detection and handling, which is costly and inefficient.

Innovation Solution

Implementing an effective address (EA) based load-store unit that uses an effective address directory (EAD) and effective real translation (ERT) table to detect LHS situations without real addresses, enabling store forwarding and reducing chip area and power consumption by tracking only EAs, allowing for 0-cycle store forwarding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If real addresses are used for LHS detection and handling, then hazard detection accuracy is improved, but chip area and power consumption increase

Engineering Contradiction:
Improvehazard detection accuracyVSAvoidchip area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent extracts only the necessary effective address information from the full address translation process. Instead of using complete real addresses for LHS detection, the system uses effective addresses combined with ERT indices, removing the unnecessary overhead of full address translation while maintaining detection accuracy.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The address detection mechanism is segmented into two parts: effective address (EA) and ERT index. This segmentation allows the system to detect LHS hazards using a combination of these two elements rather than requiring complete real address translation, thereby reducing chip area while maintaining detection precision.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If real addresses are used for LHS detection and handling, then hazard detection accuracy is improved, but power consumption increases

Engineering Contradiction:
Improvehazard detection accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by stationary object

Solution Approach 1:

The patent extracts only the necessary effective address information from the full address translation process. Instead of using complete real addresses for LHS detection, the system uses effective addresses combined with ERT indices, removing the unnecessary overhead of full address translation while maintaining detection accuracy.

Inventive Principle:
Principle #2Taking out (Extraction)

3Productivity

If store forwarding is implemented without stalling load instructions, then processor performance is improved, but hazard detection complexity increases

Engineering Contradiction:
Improveprocessor performanceVSAvoidhazard detection complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent performs preliminary hazard detection by checking the EAD and ERT table before executing load instructions. This preliminary action identifies potential LHS hazards in advance, allowing the system to forward store data directly to load instructions without stalling the pipeline, thus improving performance while managing complexity through early detection.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback mechanisms where the EAD and ERT table continuously monitor address relationships between store and load instructions. This feedback enables dynamic store forwarding decisions based on detected hazard patterns, allowing performance optimization without excessive complexity through intelligent control.

Inventive Principle:
Principle #23Feedback

4Area of stationary object

If effective address based detection is used instead of real addresses, then chip area is reduced, but detection capability may be limited

Engineering Contradiction:
Improvechip areaVSAvoiddetection capability
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent merges effective address information with ERT index information to create a composite detection key. This combination compensates for the limitations of using only effective addresses by incorporating the ERT index, which provides additional identification information. The merged approach maintains detection capability while avoiding the need for full real address translation, thus reducing chip area.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10579387B2Efficient store-forwarding with partitioned FIFO store-reorder queue in out-of-order processor
Publication Date: 2020.03.03 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10579387B2 patent drawing
  • US10579387B2 patent drawing
  • US10579387B2 patent drawing

AI summary

Technical solutions are described for executing one or more out-of-order (OoO) instructions by a processing unit. The execution includes detecting, by a load-store unit (LSU), a load-hit-store (LHS) in an out-of-order execution of the instructions, the detecting based only on effective addresses. The detecting includes determining an effective address associated with an operand of a load instruction. The detecting further includes determining whether a store instruction entry using said effective address to store a data value is present in a store reorder queue, and indicating that an LHS has been detected based at least in part on determining that store instruction entry using said effective address is present in the store reorder queue. In response to detecting the LHS, a store forwarding is performed that includes forwarding data from the store instruction to the load instruction.