Dynamic Scheduling for Low-Latency SIMD Data Processing
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Solution Overview
Problem
Current processing systems for digital audio on parallel processors face challenges in reducing latency and efficiently scheduling repeated processing steps, particularly in real-time applications where missed samples or processing delays result in noticeable effects, and existing technologies do not effectively consider priority or execution deadlines when dynamically scheduling data samples.
Innovation Solution
The system employs a memory and processors configured to dynamically schedule data samples associated with chains or graphs of data processors, using a scheduling blueprint to manage tasks and resources, and a parallel distributed scheduler to assign tasks based on priority, execution deadlines, and resource availability, reducing latency by optimizing processing across multiple processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional CPUs or DSPs are used for real-time digital audio processing, then processing can be performed sequentially with simple control logic, but processing speed and throughput are limited
Solution Approach 1:
The patent segments the processing workload into discrete tasks organized in computation graphs, where each node represents a specific processing operation. This allows parallel execution across multiple processor cores while maintaining manageable control complexity through structured task decomposition.
Solution Approach 2:
The patent implements dynamic scheduling that adapts to varying processing requirements in real-time. The scheduler dynamically assigns tasks to available processor cores based on current system state, enabling flexible resource utilization without requiring complex static control logic.
2Productivity
If GPUs with SIMT architecture are used to increase parallel processing throughput, then processing speed improves, but latency increases due to compute core design and hardware scheduler overhead
Solution Approach 1:
The patent performs preliminary configuration of computation graphs and task dependencies before execution. This pre-processing allows the runtime scheduler to efficiently dispatch tasks without excessive overhead, reducing latency while maintaining high throughput through parallel execution.
Solution Approach 2:
The patent introduces a software layer that acts as an intermediary between the host CPU and the parallel processing units. This software scheduler manages task queues and coordinates execution, abstracting away the complexity of direct hardware control while enabling fine-grained latency optimization.
3Loss of time
If dynamic scheduling based on priority and execution deadlines is implemented, then latency is reduced and real-time performance improves, but system complexity increases
Solution Approach 1:
The patent changes the parameter space by representing tasks with explicit priority levels and execution deadline attributes. This parameterization enables the scheduler to make deterministic scheduling decisions based on simple comparison operations, reducing the complexity of real-time decision-making while achieving low latency.
4Productivity
If multiple processing chains or graphs are executed concurrently, then processing efficiency and resource utilization improve, but scheduling complexity and resource management difficulty increase
Solution Approach 1:
The patent segments multiple processing chains into independent computation graphs with well-defined interfaces and data dependencies. This segmentation allows the scheduler to manage each graph separately while coordinating resource allocation across graphs, reducing overall scheduling complexity through modular organization.
Data Source
AI summary
An apparatus for parallel processing includes a memory and one or more processors, at least one of which operates a single instruction, multiple data (SIMD) model, and each of which are coupled to the memory. The processors are configured to process data samples associated with one or multiple chains or graphs of data processors, which chains or graphs describe processing steps to be executed repeatedly on data samples that are a subset of temporally ordered samples. The processors are additionally configured to dynamically schedule one or multiple sets of the samples associated with the one or multiple chains or graphs of data processors to reduce latency of processing of the data samples associated with a single chain or graph of data processors or different chains and graphs of data processors.