Activation Circuit Using Near-Zero-Vth NMOS for Low-Leakage Drive Enable
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Solution Overview
Problem
Activation circuits face challenges in reducing area and current consumption while managing variations in transistor threshold voltages and gate-induced drain leakage (GIDL), leading to increased size and current consumption.
Innovation Solution
An activation circuit utilizing an N-type MOS transistor with a threshold voltage near 0 V and a resistor between the source and ground, where the drain potential is controlled by a first signal from the drive target, and the activation signal transmission is controlled based on this potential, minimizing current consumption and GIDL influence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If design margins are provided for resistance and current consumption in consideration of variations among transistors, then reliability is improved, but area increases and current consumption increases
Solution Approach 1:
The patent changes the threshold voltage parameter of the NMOS transistor to be approximately 0V, which fundamentally alters the transistor's operating characteristics. This parameter change eliminates the need for design margins related to threshold voltage variations, thereby reducing both area and current consumption while maintaining reliability.
Solution Approach 2:
The patent implements a feedback mechanism where the drain potential controls the transmission of the activation signal. The drain potential is controlled by a first signal from the drive target, and this potential in turn controls whether the second signal (activation signal) is transmitted. This feedback loop automatically adjusts signal transmission based on the actual operating conditions, eliminating the need for conservative design margins.
2Reliability
If design margins are provided for resistance and current consumption in consideration of variations among transistors, then reliability is improved, but current consumption increases
Solution Approach 1:
By changing the threshold voltage parameter to approximately 0V, the transistor operates in a regime where small potential changes can control signal transmission. This eliminates the need for large design margins for current consumption, reducing energy usage while maintaining reliable operation despite transistor variations.
Solution Approach 2:
The feedback control mechanism using drain potential automatically regulates current consumption. When the drive target is activated, the drain potential changes to stop transmission of the activation signal, thereby reducing current consumption. This dynamic control eliminates the need for conservative current consumption margins.
3Reliability
If margins are considered for transistor variations, then reliability is improved, but device complexity increases
Solution Approach 1:
By selecting a transistor with a specific threshold voltage parameter (approximately 0V), the patent simplifies the circuit design and operation. This parameter choice naturally handles transistor variations without requiring complex compensation circuits or multiple transistors, thereby reducing device complexity while maintaining reliability.
Solution Approach 2:
The feedback mechanism using drain potential provides automatic adjustment that simplifies the overall device structure. Instead of using complex circuits to accommodate transistor variations, the feedback loop automatically compensates for variations, reducing device complexity while ensuring reliable operation.
4Area of stationary object
If Native-NMOS is used for area reduction and current consumption reduction, then area decreases and current consumption decreases, but GIDL influence increases
Solution Approach 1:
The feedback control using drain potential actively manages GIDL influence. By controlling the drain potential based on signals from the drive target, the circuit dynamically adjusts operating conditions to minimize GIDL effects while maintaining the area and current consumption benefits of Native-NMOS transistors.
Solution Approach 2:
The patent changes the operating parameters of the Native-NMOS transistor, specifically controlling the drain potential to manage GIDL influence. By adjusting the drain potential based on feedback from the drive target, the circuit reduces GIDL effects while preserving the compact size and low current consumption characteristics of Native-NMOS technology.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves area reduction and current consumption minimization, effectively eliminating the need for design margins and reducing GIDL impact, ensuring reliable activation signal restriction.
Implementation Method 1
designing of an activation circuit has to be provided with margins for resistance and current consumption in consideration of variations among elements such as transistors (for example, Native-NMOS)... in consideration of gate-induced drain leakage (GIDL)
Data Source
AI summary
An activation circuit which can realize both of area reduction and current consumption reduction by more preferred embodiments. The activation circuit has an N-type MOS transistor having a gate terminal connected to a ground and having a threshold voltage in a vicinity of 0 V and a resistor interposed between a source terminal of the MOS transistor and a ground, wherein an electric potential of a drain terminal of the MOS transistor is controlled depending on a first signal output from a device serving as a drive target, and transmission of a second signal for activating the device is controlled depending on the electric potential of the drain terminal.