Active Chip Package Substrate Embedding via Thermal Compression
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Solution Overview
Problem
Current microelectronic packaging methods face challenges in embedding active chips due to their complex internal structures and thickness, leading to issues like air bubbles and increased package size, especially when using flip chip technology, and existing methods are complex and inefficient for achieving high-density, compact, and lightweight packaging.
Innovation Solution
The method involves bonding active bare chips to supporting boards with temporary films, adding a prepreg dielectric sheet, and using thermal-compression to embed the chips into the sheet, forming a core board, which simplifies the process and avoids packaging-related defects like air bubbles, allowing for simultaneous embedding of multiple chips and improved integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flip chip technology is used to connect packaged chips to substrates, then electrical connections can be established, but air bubbles form in the gaps between bumps and the package size increases
Solution Approach 1:
The patent applies preliminary action by forming recesses in the substrate before embedding the chip. These recesses are pre-configured to match the bump pattern, allowing the dielectric material to be deposited and cured in place, eliminating gaps where air bubbles could form. The chip is then embedded into these pre-prepared recesses, ensuring complete filling without voids.
Solution Approach 2:
The patent uses a dielectric layer as an intermediary material that fills the spaces between bumps and provides a continuous medium for electrical connections. This dielectric layer is deposited over the bumps and cured to form a solid matrix that eliminates air gaps while maintaining electrical integrity through the embedded chip.
2Reliability
If chips are packaged before embedding, then they can be connected to substrates, but the package structure becomes large and complex
Solution Approach 1:
The patent inverts the conventional approach by embedding the bare chip directly into the substrate first, and then forming the dielectric layer and connections around it. Instead of attaching a pre-packaged chip to the substrate surface, the chip is embedded within the substrate structure, allowing the dielectric to be formed in situ and eliminating the need for separate packaging components.
Solution Approach 2:
The patent merges the chip embedding process with the substrate formation process. The dielectric layer is deposited and cured simultaneously with the chip embedding, combining what would traditionally be separate steps into one integrated process. This merging eliminates the need for separate packaging structures and reduces overall package size.
3Productivity
If multiple chips are embedded simultaneously into the substrate, then integration density improves, but the embedding process becomes more complex
Solution Approach 1:
The patent applies segmentation by dividing the substrate into multiple recesses, each designed to accommodate a specific chip. This segmentation allows multiple chips to be embedded simultaneously in predetermined positions without interfering with each other. The dielectric layer is then deposited uniformly across all recesses, curing each chip embedding independently while maintaining overall process simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables direct embedding of active bare chips, reducing manufacturing complexity, avoiding air bubbles, and achieving high integration density with improved electrical connections and a lightweight, compact package structure, while being compatible with planar semiconductor processes.
Implementation Method 1
adding at least one layer of prepreg dielectric sheet between the upper supporting board and the lower supporting board, the total thickness of the prepreg dielectric sheet being greater than the thickness of the upper active chip or the thickness of the lower active chip; bonding the upper supporting board, the at least one layer of prepreg dielectric sheet, and the lower supporting board by thermal-compression such that the at least one upper active chip and the at least one lower active chip are embedded into the prepreg dielectric
Data Source
AI summary
An active chip package substrate and a method for preparing the same. The active chip package substrate includes: a core board; at least one upper active chip, embedded in the core board and having an active surface facing toward a lower surface of the core board, the upper active chip being an active bare chip; and at least one lower active chip, embedded in the core board and having an active surface facing toward an upper surface of the core board, the lower active chip being an active bare chip.