Active Clamp Circuit for ADC Oscillation Without Dynamic Range Loss
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Solution Overview
Problem
High-resolution analog to digital converters (ADCs) in radar and communication systems face oscillation issues due to large input signals, leading to system shutdown and significant degradation in receiver dynamic range, which existing gain control circuits and architecture modifications have not adequately addressed.
Innovation Solution
An active clamp circuit using diode-connected transistors in inverse parallel configuration to provide a positive and negative conducting path, clamping differential voltages outside a defined range, thereby limiting energy and preventing oscillations without significantly affecting small signal linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gain control circuits are used to detect and process signals outside acceptable signal strength, then oscillation is alleviated, but receiver dynamic range is significantly degraded
Solution Approach 1:
The patent introduces an intermediary clamp circuit positioned between the ADC and subsequent processing stages. This circuit acts as a mediator that clips extreme voltage excursions before they cause oscillation, while being designed to minimally impact the dynamic range through careful selection of clamping voltage levels and circuit topology.
Solution Approach 2:
The invention changes the operational parameters of the signal path by introducing controlled voltage clamping at specific threshold levels. By adjusting the clamping voltage parameters to be just above the normal operating range but below the oscillation threshold, the system prevents limit cycles while preserving the majority of the dynamic range for valid signals.
2Reliability
If ADC architecture is modified to suppress limit cycles, then oscillation is reduced, but receiver dynamic range is significantly degraded
Solution Approach 1:
The patent extracts the oscillation suppression function from the ADC core architecture and places it in a separate, dedicated clamp circuit. This extraction allows the ADC to maintain its original high-dynamic-range architecture while the external clamp circuit handles limit cycle suppression, avoiding the dynamic range degradation that would result from modifying the ADC's internal architecture.
3Reliability
If conventional diode limiters are used to clamp voltage, then large signal oscillation is prevented, but small signal linearity is significantly affected
Solution Approach 1:
The patent applies local quality by making the clamping action highly selective in its activation. The clamp circuit is designed with specific voltage thresholds that ensure it remains inactive during small signal operation, preserving linearity, and only activates locally at the extreme voltage excursions where oscillation occurs. This is achieved through careful biasing and transistor sizing to create a sharp transition from transparent to clamping state.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The active clamp circuit effectively limits energy, preventing oscillations and maintaining dynamic range, with clamping voltages dependent on transistor turn-on voltages and number, achieving a sharper clamp knee and reduced small signal suppression compared to conventional diode limiters.
Implementation Method 1
two sets of diode connected transistors connected in inverse parallel across an output of the component for providing a positive conducting path and a negative conducting path
Implementation Method 2
Each set of diode connected transistors is configured to clamp its associated current path in response to a differential voltage (Vout) at the output of the component being outside of a voltage range defined by Vclampn and Vclampp
Data Source
AI summary
An active clamp circuit for electronic components includes two sets of diode connected transistors that are inversely connected in parallel across an output of the component for providing both positive and negative differential conducting paths. The diode connected transistors cooperatively operate to limit a differential output voltage between the positive and negative conducting paths. An emitter follower buffer includes the clamp circuit and is configured to limit RF energy incident to an analog to digital converter (ADC). The emitter follower buffer includes two input transistors having their emitters each connected to at least one diode connected transistor connected to the clamp circuit. A receiver includes the differential amplifier and an analog to digital converter. A method for limiting the energy of analog signals in the receiver includes the step of operating the clamp circuit to limit the analog signals transmitted to the analog to digital converter (ADC).