Analogue/Digital Conversion TRIZ Cases

Digital timing reference and in-coil ADC clocking improve MRI receiver signal quality while cutting cabling, interference, and setup burden.

Periodic sampling with frequency-domain conversion and calibration removes artifacts to calculate accurate exposure metrics with low memory use.

A switched-capacitor voltage transformer raises EEG input voltage before A/D conversion to cut noise contribution and current draw.

Interleaved sampling channels and frequency-domain delay compensation enable accurate wideband signal reconstruction and channel time-delay calculation.

Multiple phase detectors split high-rate CDR into lower-speed sampling paths, easing circuit speed demands while averaging noise.

By placing the index bar on the same optical track, this encoder cuts reflective system complexity and size while preserving accurate angular position signals.

Dynamic DAGC storage and restoration cuts quantization error, helping mobile stations detect enhanced pilot signals for accurate positioning.

Multiple gain-channel ADCs replace VGA-based analog front ends to extend dynamic range and improve back-wall flaw detection.

Buffer-amplifier voltage equalization suppresses oscillator dithering overshoot, reducing frequency spikes and EMI issues during switching.

Cascaded auto-zero amplifier paths stabilize SAR ADC operation despite cycle-to-cycle gain and bandwidth variation.

Multiple scaled A/D channels replace complex analog gain stages to extend dynamic range and improve ultrasonic fault detection accuracy.

A capacitive feedback array injects time-independent charge to cut clock-jitter noise folding and improve continuous-time modulator stability.

Using sign bits plus confidence values, this phase detector improves low-SNR timing recovery and cuts loss-of-lock in hard-drive read channels.

Separate transition and signal noise shaping suppress plops and clicks during DC blocking capacitor charging without destabilizing PWM output.

Multi-phase clock latching and decoding speeds solid-state image sensor ADCs by reducing counter bit width without sacrificing precision.

Weighted differences between adjacent samples guide sampling clock phase adjustment, improving striped-image capture accuracy and image quality.

A secondary PWM subtracts its output from twice the input to cancel non-linear error and sharply cut class D amplifier distortion.

A hybrid AGC loop switches between zero forcing and LMS feedback by Nyquist energy threshold to improve gain control across varying conditions.

Switch-controlled offset capacitors cancel comparator offset in sampled-data circuits, improving zero-crossing precision without higher power.

A non-binary DAC relaxes matching requirements in power-on amplifier offset trim while preserving accurate compensation.

A capacitive bypass sends input signal current directly to a switching load, reducing transconductance modulation and ADC output error.

A peaking circuit boosts switching current during track-to-hold transitions, cutting distortion and improving low-frequency SFDR by 15 dB.

A multiplexer-controlled resistor and transmission-gate network stabilizes oscillator voltage by reducing impedance-driven deviation.

A second capacitor adds a low-impedance charge path in the sampling phase, cutting frequency-dependent harmonic distortion in ADC track-and-hold circuits.

Coarse shift and fine multiply blocks convert logarithmic gain quickly over low-bandwidth RFIC links, preserving signal fidelity and power.

Segmented input and output delay stages hold and shift pulse edges to generate multiple signals with timing finer than one clock cycle.

Inverse-parallel diode-connected transistors clamp large differential signals to stop ADC oscillation while preserving receiver dynamic range.

Control circuitry shifts power between the PGA and ADC as gain changes, cutting acquisition power while preserving noise performance.

A shifted symbol-period sampling scheme finds the best receiver phase without full oversampling, reducing wireless hardware cost and power use.

A dual-feedback sampling circuit uses amplified error correction and multiple capacitors to attenuate KTC noise and preserve analog signal accuracy.

Sequentially rotating and resetting three SDM feedback elements cuts mismatch-driven in-band noise and improves sampled data integrity.

Self-bias and external bias switching isolates the bias circuit from CMOS switching noise while preserving high-speed A/D comparator operation.

Binary-controlled RSFQ stages and inverters create selectable digital phase delays without giving up ultrafast Josephson-junction circuit speed.

Switch analog and ADC paths by baud rate to balance power and data recovery.

A drive circuit uses an operational amplifier to compare voltages and control a MOS transistor for consistent LED luminance.

Decoupling the short data acquisition cycle from the long forwarding cycle enables wide-range frequency noise removal without delaying control signals.

Paired capacitors maintain equal total capacitance across sampling and holding phases to stabilize operational amplifier common-mode input voltage.

A correction circuit compares digitized and analog current signals to align digital representations with physical reality.

Digital sub-regulators segment power delivery via variable-impedance switches, reducing energy waste in low-speed processors.

Segmented capacitor switch circuit adjusts column amplifier gain to reduce parasitic capacitance and increase frame rate.

A DAC circuit generates test signals to measure ground leakage resistance in land seismic systems.

An apparatus measures output voltages from two voltage dividers to calculate adapter attributes using analog-to-digital converters.

A MEMS resonator-based oscillator uses a multiplexer to select calibration signals for frequency stability.

Segmenting protection paths across multiple DAC units reduces the equivalent time constant, preventing slow output times during electrostatic discharge events.

Active resistance controller counters temperature-induced electrical property changes by adjusting resistance via proportional to absolute temperature source.

Sorting current sources by measured level determines switching sequences that align integral non-linearity trends, resolving echo cancellation mismatch.

A solid-state image pickup apparatus reads pixel signals from multiple sensitivity systems and amplifies them at varying rates to synthesize expanded dynamic range.

Thick-oxide MOSFET clamps bias via adaptive references to shield thin-oxide transistors from over-voltage damage while preserving signal linearity.

A bias voltage system adjusts capacitance dynamically to deliver stable power to active devices under rapid load changes.