Sample-and-Hold Peaking Circuit for Low-Frequency SFDR
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Solution Overview
Problem
Conventional sample-and-hold circuits for analog-to-digital converters lack 'peaking currents' necessary for smooth transitions from track to hold, leading to signal distortion dependent on signal frequency and transition time, which is influenced by the magnitude of switching current.
Innovation Solution
A track-and-hold circuit with a bi-directional current source and a peaking circuit that includes capacitors, inductors, or synthetic inductors to provide a high current during transitions from track to hold, ensuring sufficient current for accurate signal capture and minimizing distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional sample-and-hold circuits are used without peaking currents, then the circuit structure remains simple, but signal distortion increases during transitions from track to hold
Solution Approach 1:
The peaking circuit is activated in advance during the transition from track to hold mode to generate a current peak before the main switching occurs. This preliminary action ensures that the switching transistors have sufficient drive current available exactly when needed, enabling smooth transitions and minimizing signal distortion without requiring the entire circuit to be complex.
Solution Approach 2:
The peaking current is generated locally at the switching transistor gates through dedicated peaking circuits (capacitors connected to gate nodes or separate peaking transistors). This local enhancement provides high current precisely where needed during switching transitions without complicating the entire sample-and-hold circuit structure, resolving the contradiction between simplicity and performance.
2Speed
If the switching current magnitude is increased to reduce transition time, then the transition speed improves, but the circuit complexity and distortion increase
Solution Approach 1:
The peaking circuit operates periodically during each track-to-hold transition, generating a temporary current peak only when needed. Using capacitors that charge during track mode and discharge during hold mode, or peaking transistors activated by transition signals, the circuit provides high switching current momentarily to achieve fast transitions without maintaining high complexity continuously.
Solution Approach 2:
The peaking current is prepared in advance through capacitor charging or peaking transistor pre-activation before the main switching event. This preliminary preparation ensures that when the transition occurs, the high current is already available, achieving fast transition times without requiring the circuit to continuously maintain complex high-current switching paths.
3Measurement precision
If peaking circuits with capacitors and inductors are added to enhance SFDR, then the Spurious-Free Dynamic Range improves by 15 dB, but the device complexity increases
Solution Approach 1:
The essential peaking function is extracted from a full LC resonant circuit and implemented using only the necessary minimal components. Capacitors are connected directly to transistor gate nodes to provide local peaking, or simple peaking transistors with resistor-capacitor networks are used instead of complex inductor-based circuits. This extraction achieves the 15 dB SFDR improvement while minimizing the added complexity.
Solution Approach 2:
Capacitors serve as intermediary elements that store energy during track mode and release it as peaking current during hold mode. Alternatively, peaking transistors act as intermediaries that amplify the transition signal to generate the required current peak. These intermediary components enable the SFDR enhancement without requiring direct complex LC circuitry, reducing overall device complexity while maintaining performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of a peaking circuit with capacitors, inductors, or synthetic inductors in the track-and-hold circuit enhances the Spurious-Free Dynamic Range (SFDR) by 15 dB at low frequencies and ensures accurate signal holding by providing a large current during transitions, reducing distortion.
Implementation Method 1
a peaking circuit that causes the current through at least one of the transistors to exceed a threshold for a predetermined period when the track-and-hold circuit transitions from track to hold
Implementation Method 2
The peaking circuit comprises a plurality of inductors, wherein each inductor is coupled to the control electrode of at least one transistor of one of the first and second differential input circuits
Implementation Method 3
each synthetic inductor further comprises a peaking transistor; and an resistor/capacitor (RC) network that is coupled to the control electrode of the peaking transistor
Data Source
AI summary
A track-and-hold or sample-and-hold (S/H) circuit for an analog-to-digital converter (ADC) is provided. A difference between the disclosed S/H circuit and conventional S/H circuits is the use of a peaking circuit. This peaking circuit generally provides increased current to switching transistor when transitioning between track and hold which can increase the Spurious-Free Dynamic Range (SFDR) as low frequencies, by as much as 15dB.