Continuous-Time Sigma-Delta Modulator With Jitter-Insensitive Feedback
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Continuous-time sigma-delta modulators face performance limitations due to clock jitter, quantiser metastability, and non-linearity of the integrator, which degrade noise performance and stability, especially in high-frequency and high-bandwidth applications.
Innovation Solution
A sigma-delta modulator design that uses a capacitive array with switch units connecting capacitors to either a first or second voltage level, controlled by a digital integrator to provide time-independent charge injection, reducing jitter sensitivity and noise folding, and incorporating a multi-bit digital integrator for improved noise handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a continuous-time sigma-delta modulator is used to achieve power saving and higher input bandwidth, then power consumption is reduced and bandwidth is increased, but clock jitter causes noise that directly modulates the feedback signal and degrades performance
Solution Approach 1:
The patent replaces the traditional voltage-based feedback mechanism with a current-based feedback mechanism. The feedback signal is provided as a current from a current source rather than a voltage, which fundamentally changes how the feedback interacts with the summing junction. This substitution makes the system insensitive to clock jitter because the current feedback is not modulated by timing variations in the same way voltage feedback is.
Solution Approach 2:
The patent changes the fundamental parameter of the feedback signal from voltage to current. By providing feedback current instead of feedback voltage, the system alters the physical domain in which the feedback operates. This parameter change resolves the jitter sensitivity issue while maintaining the continuous-time architecture's power and bandwidth advantages.
2Manufacturing precision
If the feedback signal voltage limits are used to set the input range, then the modulator operates within defined voltage boundaries, but clock jitter causes the feedback signal to be modulated and adds noise to the input signal
Solution Approach 1:
The patent substitutes voltage feedback with current feedback, replacing the voltage-based mechanism that is susceptible to jitter-induced modulation with a current-based mechanism that is inherently insensitive to such modulation. The current source provides feedback current that flows through the summing junction without being modulated by clock transitions.
Solution Approach 2:
The patent introduces a current source as an intermediary element between the digital output and the summing junction. This current source acts as a mediator that converts the digital feedback into an analog current signal that is independent of clock jitter, thereby eliminating the harmful noise modulation effect.
3Measurement precision
If oversampling is used to spread quantisation noise over a wider frequency range, then noise magnitude decreases over the frequency range of interest, but the sampling frequency required for high resolution is typically too high to be practicably realisable
Solution Approach 1:
The patent replaces the traditional voltage feedback mechanism with current feedback, which fundamentally alters the noise characteristics of the system. The current feedback approach reduces jitter-induced noise without requiring increased sampling frequencies, thereby achieving high-resolution performance at practical sampling rates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves improved noise performance and stability by making the feedback loop insensitive to clock jitter and reducing noise folding, while maintaining a continuous-time implementation with reduced power consumption and increased bandwidth.
Implementation Method 1
a sigma-delta modulator having a node arranged to receive a current flow that is representative of the voltage level of the input signal and on whose voltage the digital output signal is dependent and a reference capacitor which can be continuously recharged to a reference voltage by a current source
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
A sigma-delta modulator for forming a digital output signal representative of a voltage level of an input signal, the sigma delta modulator having a node arranged to receive a current flow that is representative of the voltage level of the input signal and on whose voltage the digital output signal is dependent, the sigma-delta modulator comprising a plurality of capacitive elements for smoothing the current flow, each capacitive element being connected at one end to the node and at its other end to a respective switch unit and a plurality of switch units, each switch unit being arranged to connect the respective one of the capacitive elements to either a first voltage level or a second voltage level in dependence on the voltage at the node so as to provide feedback that affects the voltage at the node.