Differential Amplifier Bias Switching for Noise-Isolated A/D Comparison
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional differential comparators in A/D converters suffer from switching noise due to parasitic capacitances in CMOS switches, which affects the output and hinders high-speed operation.
Innovation Solution
A differential amplifier design incorporating a differential transistor pair, current sources, bias circuits, and self-bias switches to manage noise by switching between self-bias and external bias states, isolating the bias circuit from noise during input transitions and enabling immediate transition to amplification mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If CMOS switches are used in the differential comparator, then the circuit can operate at high speed, but parasitic capacitances cause switching noise that degrades output quality
Solution Approach 1:
The patent segments the biasing function into two independent parts: self-bias switches (SW1-SW4) that remain ON during signal processing to maintain stable bias points, and an external bias switch (SW5) that is turned OFF during operation to isolate the bias circuit from switching noise. This segmentation allows the circuit to simultaneously achieve high-speed operation and noise reduction.
Solution Approach 2:
The bias circuit performs preliminary action by pre-establishing stable bias voltages for the differential transistor pair before the switching noise occurs. The self-bias switches are turned on in advance to set the operating point, and the external bias switch is turned off before the noisy switching operation to prevent noise injection into the bias circuit.
2Measurement precision
If the bias circuit is continuously connected to control current sources, then current can be precisely controlled, but the bias circuit becomes vulnerable to switching noise from input terminals
Solution Approach 1:
The patent implements dynamic switching of the external bias switch (SW5) based on the operational phase. During signal processing, SW5 is OFF to isolate the bias circuit from noise while self-bias switches maintain current control. During reset or calibration phases, SW5 can be turned ON to re-establish precise bias control. This dynamic approach allows the system to adaptively balance noise isolation with current control precision.
Data Source
AI summary
Connected to a differential transistor pair are a load current source and a tail current source. A bias circuit controls current generated by the load current source. A first self-bias switch is provided between a gate and a drain of a first input transistor; and a second self-bias switch is provided between a gate and a drain of a second input transistor, where the first input transistor and the second input transistor constitute the differential transistors pair. An external bias switch is provided between the bias circuit and the load current source.