Sampling Clock Phase Adjustment for Accurate ADC Image Capture
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Solution Overview
Problem
Conventional methods for selecting the phase of the sampling clock in sampling circuits, such as ADCs, are not accurate, leading to degraded image quality, especially when dealing with images composed of numerous stripes.
Innovation Solution
A device and method that calculate differences between adjacent sampled values, generate a calculated value by weighting these differences, and adjust the sampling clock phase to maximize the calculated value, ensuring a predetermined condition is met, thereby improving the phase selection accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the sum of absolute difference (SAD) method is used to select sampling phase, then the calculation is simple, but the measurement precision deteriorates especially for striped images
Solution Approach 1:
The patent transforms the calculation from using absolute differences to using squared differences. This parameter change in the mathematical operation fundamentally alters the weighting of differences, giving more emphasis to larger deviations and thereby improving phase selection accuracy while maintaining computational feasibility through the mathematical properties of squaring operations.
2Productivity
If conventional SAD calculation is used, then the computational complexity is low, but the image quality deteriorates due to inaccurate phase selection
Solution Approach 1:
The patent changes the calculation parameter from absolute difference to squared difference, which fundamentally improves the sensitivity to phase errors. This parameter transformation maintains computational efficiency while dramatically improving image quality by providing more accurate phase selection that properly weights larger deviations in the sampled signal.
Data Source
AI summary
Methods for adjusting a sampling clock of a sampling circuit and related apparatuses are disclosed. One proposed method includes: calculating difference between adjacent sampled values, generated from the sampling circuit by sampling an incoming signal based on the sampling clock, to obtain a plurality of differences; performing a predetermined calculation on the differences to generate a calculated value, the differences including a first difference with a first absolute value and a second difference with a second absolute value less than the first absolute value, and the predetermined calculation causing that a ratio of component of the calculated value contributed by the first difference to component of the calculated value contributed by the second difference to be greater than a ratio of the first absolute value to the second absolute value; and adjusting phase of the sampling clock so that the calculated value generated by the predetermined calculation satisfies predetermined conditions.