Solid-State Image Sensor ADC Using Multi-Phase Clock Decoding
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Solution Overview
Problem
Existing solid state image capture devices face limitations in achieving high-speed analog-to-digital (AD) conversion due to the operation speed of the counter unit, requiring higher speed clocks to shorten AD conversion time.
Innovation Solution
The implementation of a multi-phase clock system with a constant phase difference, where the logic states of the multi-phase clocks are latched and decoded to obtain a bit string with time information, allowing the counter unit to perform counts during the comparison process and reducing the bit width of the counter unit, thereby enabling faster AD conversion without being limited by its operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If higher speed clocks are used to operate the counter unit, then AD conversion time is shortened and processing speed is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent divides the counter unit into multiple parallel counter units, each handling a portion of the bit width. This segmentation allows the system to achieve high-speed AD conversion without requiring excessively high clock speeds for a single counter, thereby reducing overall system complexity and power consumption while maintaining high productivity.
Solution Approach 2:
The patent transitions from increasing clock frequency (one dimension) to increasing the number of parallel counter units (another dimension). This dimensional shift allows the system to achieve faster AD conversion through parallel processing rather than relying solely on higher speed clocks, thus resolving the contradiction between speed and complexity.
2Measurement precision
If the bit width of the counter unit is increased to improve conversion precision, then measurement precision is improved, but the operation speed of the counter unit decreases
Solution Approach 1:
The patent segments the total bit width into multiple smaller portions, with each counter unit handling a specific portion. This segmentation enables each counter unit to operate at high speed while the aggregate system achieves high precision through the combined output of multiple parallel units, effectively resolving the contradiction between precision and speed.
Solution Approach 2:
The patent merges the outputs of multiple parallel counter units to achieve the total bit width required for high-precision AD conversion. By combining the results from multiple fast-operating counters, the system achieves both high speed and high precision, overcoming the limitation of single counter units where increased bit width reduces operation speed.
Data Source
AI summary
A solid state image capture device includes a pixel array unit having unit pixels including a photoelectric conversion element disposed in a matrix shape and analog/digital conversion means for converting an analog pixel signal read from the unit pixel of the pixel array unit into digital data. The analog/digital conversion means includes a comparator unit for converting a magnitude of the pixel signal into information in a time axis direction, a counter unit for performing a count process during a time period from a start time of a comparison process at the comparator unit to an end time of the comparison process, a multi-phase clock generate unit for generating multi-phase clocks having a constant phase difference, a latch unit for latching logic states of the multi-phase clocks, and a decode unit for decoding latch data of the latch unit to obtain a value lower than a count value.