Sample Hold Circuit Stabilizing Op-Amp Gain via Paired Capacitors
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Solution Overview
Problem
Pipeline and cyclic analog-to-digital converters face errors due to variations in common-mode input voltage affecting the operational amplifier's gain and slew rate, leading to unstable output in A/D conversion processes.
Innovation Solution
A sample hold circuit is designed with paired capacitors connected to the operational amplifier's inverting and non-inverting inputs, ensuring constant common-mode input voltage during the sampling phase and accurate voltage holding by maintaining equal total capacitance in both phases, thereby stabilizing the op-amp's operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional sample hold circuit is used without paired capacitors, then the circuit structure is simple, but the common mode input voltage to the op-amp varies causing gain and slew rate variations
Solution Approach 1:
The capacitor network is segmented into multiple pairs of first and second capacitors, with each pair connected to the inverting and non-inverting inputs respectively. This segmentation allows independent control of capacitance values to maintain equal total capacitance while providing different voltage division ratios, thereby stabilizing the common mode input voltage without requiring a completely new circuit architecture.
Solution Approach 2:
The invention changes the parameters of the capacitor network by using multiple pairs of capacitors with different capacitance values. By adjusting the capacitance values while maintaining equal total capacitance, the voltage division ratio changes to compensate for input voltage variations, thereby stabilizing the common mode input voltage to the op-amp and ensuring stable gain and slew rate characteristics.
2Measurement precision
If the total capacitance of first and second capacitors is made equal in holding phase, then accurate voltage holding is achieved, but the circuit design becomes more constrained
Solution Approach 1:
The capacitor configuration is made dynamic by using switches to connect and disconnect different capacitor pairs during sampling and holding phases. During the sampling phase, first capacitors are connected to the input voltage while second capacitors are connected to a predetermined voltage. During the holding phase, the connections are switched to maintain equal total capacitance. This dynamic reconfiguration enables accurate voltage holding while providing design flexibility through multiple capacitor pair options.
3Reliability
If paired capacitors with equal total capacitance are used in both phases, then common mode input voltage is stabilized, but the capacitor selection and design becomes more complex
Solution Approach 1:
The capacitor pairs serve multiple functions: they provide voltage division to stabilize the common mode input voltage, they maintain equal total capacitance for accurate voltage holding, and they enable dynamic reconfiguration between sampling and holding phases. By designing the capacitor network with these multiple functions integrated, the invention achieves stable common mode input voltage while the standardized paired structure simplifies the manufacturing process through reusable capacitor pairs.
Data Source
AI summary
A sample hold circuit includes an op-amp, first capacitors provided on an inverting side of the op-amp and second capacitors provided on a non-inverting side. The sample hold circuit is configured such that a total capacitance of the first and second capacitors to which an input voltage is applied in a sampling phase is equal to that of the first and second capacitors to which the input voltage is applied in a holding phase, a total capacitance of the first capacitors to which the input voltage is applied in the holding phase is equal to that of the second capacitors to which the input voltage is applied in the holding phase, and a total capacitance of the first capacitors to which the input voltage is applied in the sampling phase is different from that of the second capacitors to which the input voltage is applied in the sampling phase.