Shared Active Contact Layout Under Gate Isolation in MOSFET Scaling
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improvements in semiconductor devices to maintain high performance.
Innovation Solution
A semiconductor device design featuring a first and second gate electrode with spaces in between, connected by an active contact and separated by an insulating separation pattern, along with a specific arrangement of source/drain patterns and channel patterns, utilizing advanced materials and structures to enhance electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to reduce pattern size and design rule, then device density and integration are improved, but operational properties deteriorate
Solution Approach 1:
The gate electrode is divided into multiple segments (first gate electrode and second gate electrode) separated by an insulating separation pattern. This segmentation allows each gate segment to independently control adjacent source/drain regions, maintaining effective gate control despite overall device scaling, thereby preserving operational properties while enabling reduced pattern size
Solution Approach 2:
An insulating separation pattern is introduced as an intermediary element between the first and second gate electrodes. This intermediary structure prevents direct electrical connection between gate segments while allowing the active contact to extend underneath it, enabling independent gate control and maintaining device performance at scaled dimensions
2Adaptability or versatility
If gate electrodes are separated by insulating material, then independent control of adjacent transistors is improved, but connectivity between source/drain regions becomes more difficult
Solution Approach 1:
The active contact extends in the vertical dimension underneath the insulating separation pattern, allowing electrical connection between source/drain regions without requiring lateral routing around the insulating barrier. This three-dimensional contact structure maintains ease of manufacture by using standard vertical contact formation processes while achieving independent gate control through the insulating separation
Data Source
AI summary
A semiconductor device includes a first gate electrode and a second gate electrode which are each on a substrate and extend in a first direction, first and second source/drain patterns spaced apart from the first and second gate electrodes in a second direction which crosses the first direction, and an active contact in common connection with top surfaces of the first source/drain pattern and the second source/drain pattern. The active contact comprises a first portion on the first source/drain pattern and a second portion on the second source/drain pattern. The device includes an insulating separation pattern which extends in the second direction to separate the first gate electrode from the second gate electrode, and the active contact comprises a third portion which extends to a region below a bottom surface of the insulating separation pattern to connect the first and second portions of the active contact to each other.