Nanoinformatics TRIZ Cases
- Two-Level Sidewall Spacer Layout for Low-Resistance Nanosheet FETs
A two-level sidewall spacer increases epitaxial source/drain volume to cut resistance and capacitance in scaled nanosheet transistors.
- Extended Contact Structure for GAA FET Channel Control
A wraparound extended contact and fully surrounding gate improve channel depletion, cut short-channel effects, and lower contact resistance.
- Stacked MBCFET Channel Structure for Short-Channel Leakage Control
Vertically stacked channels with surround gates and recess-protrusion features curb short-channel effects, leakage, and sub-threshold swing.
- Multi-Gate GAA Transistor Layout for Leakage and Drive Current Tuning
Selective dielectric features and channel-layer counts let one GAA process balance low leakage and higher drive current across device regions.
- Strained Nanosheet Channels on SOI Without SiGe Buffer Layers
A modified SOI Si/SiGe bi-layer replaces costly SiGe buffer layers, enabling higher-quality strained nanosheet channels and faster switching.
- Nanosheet FET Structure With Asymmetric Source/Drain Layer Contact
Stacked nanosheet channels with gate-all-around control and asymmetric source/drain contact improve density while limiting short-channel effects.
- Asymmetric Source/Drain Layout for Backside Source Contact Alignment
A deeper source recess and dummy contact improve backside source contact alignment, lowering contact resistance in scaled FET fabrication.
- Deep Trench Via Connection for Misaligned Frontside-Backside Metal Wires
A deep trench via adds a horizontal connection between misaligned frontside and backside metal wires to maintain reliable chip interconnects.
- MOSFET Contact and Gate Protrusions for Short-Margin Scaling
Vertical gate and active-contact protrusions preserve short margin in scaled MOSFETs, improving interconnect reliability and process yield.
- Semiconductor Gate Isolation Features for Overlay-Accurate Metal Gate Etch
Isolation fins and dielectric helmets improve overlay tolerance and metal gate etch accuracy for gates with different critical dimensions.
- Stacked Transistor Gate Electrode Deposition for Seam-Free Gap Fill
Alternating high- and low-sticking precursors enable bottom-up work function metal deposition for seam-free gate fill and better etch control.
- GAA FET Isolation Structure With Etch-Resistant Dielectric Layer
A carbon-doped dielectric layer shields flowable-CVD oxide isolation in GAA FETs from over-etching, helping reduce junction leakage.
- Buried Epitaxial Layer in GAA Transistors for Junction Leakage
A doped buried epitaxial layer in GAA transistors suppresses parasitic channels, limits over-etch leakage, and simplifies doping.
- Nanostructure Gate Dielectric Segmentation for Vt and Mobility Tuning
A two-step gate dielectric process separates dipole and fluorine regions to tune threshold voltage while preserving carrier mobility.
- Multi-Gate Inner Spacer Structure With Air Gaps for Lower Capacitance
A composite inner spacer uses dielectric layers and air gaps to cut parasitic capacitance while preserving etch resistance in multi-gate transistors.
- Air Inner Spacer Structure for Lower Parasitic Capacitance
Removing part of the inner spacer and sealing the opening creates an air gap that cuts GAA parasitic capacitance and lifts device performance.
- Nano-FET Gate Stack Annealing for Dense Semiconductor Patterning
Oxygen-diffusion annealing in a nano-FET gate stack helps maintain precise patterning and device performance as semiconductor features shrink.