Nanosheet FET Structure With Asymmetric Source/Drain Layer Contact
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in achieving further improvements in nanosheet FETs to address scaling down issues, particularly in enhancing device density, performance, and reducing short-channel effects while maintaining manufacturing complexity and cost-effectiveness.
Innovation Solution
The development of a semiconductor device structure involving a stack of semiconductor layers with alternating first and second semiconductor layers, where the second semiconductor layers form nanosheet channels surrounded by a gate electrode, utilizing advanced fabrication processes such as epitaxial growth, double-patterning, and selective etching to create fins and gate stacks, resulting in a nanosheet transistor design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are scaled down to increase device density, then production efficiency and cost are improved, but short-channel effects and manufacturing complexity increase
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanosheet channels with gate-all-around configuration. This dimensional change enables the gate to control the channel from all directions (top, bottom, and sides), providing superior electrostatic control that mitigates short-channel effects while allowing continued scaling for higher device density
Solution Approach 2:
The patent implements a nested structure where the gate electrode completely surrounds the nanosheet channel, with the gate wrapping around the channel from all sides. This nested gate-all-around configuration provides enhanced control over the channel region, enabling better suppression of short-channel effects at scaled dimensions
2Reliability
If nanosheet FET structure is implemented to reduce short-channel effects, then device performance is improved, but fabrication process complexity increases
Solution Approach 1:
The patent divides the channel region into multiple thin nanosheet layers stacked vertically, with gate electrodes surrounding each nanosheet. This segmentation into discrete nanosheet channels provides better electrostatic control and reduced short-channel effects compared to a single thick channel, while the modular structure enables systematic fabrication
Solution Approach 2:
The patent employs preliminary patterning actions through double-patterning techniques to define the nanosheet structures before final gate formation. This preliminary structuring of the channel region enables subsequent gate-all-around formation and achieves the desired nanosheet geometry with controlled dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device density and performance by enabling fuller depletion in the channel region, reducing short-channel effects, and improving manufacturing efficiency through a more complex yet effective nanosheet FET design.
Implementation Method 1
The first source/drain epitaxial feature and the second source/drain epitaxial feature are selectively removed
Data Source
AI summary
A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.