Nano-FET Gate Stack Annealing for Dense Semiconductor Patterning
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Solution Overview
Problem
As semiconductor devices continue to reduce minimum feature sizes for increased integration density, challenges arise in efficiently forming and patterning semiconductor layers to maintain device performance and reliability.
Innovation Solution
The manufacturing process involves forming nanostructures over fins on a semiconductor substrate, using a gate-last process, and employing double-patterning or multi-patterning techniques to create nano-FETs with alternating semiconductor layers that are etched selectively, followed by the formation of STI regions and epitaxial source/drain regions to enhance device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but additional problems arise in fabricating and patterning semiconductor layers
Solution Approach 1:
The patent applies segmentation by dividing the patterning process into multiple stages through double-patterning or multi-patterning techniques. First, a mandrel layer is formed and patterned, then removed, and subsequently a spacer layer is deposited and patterned to create the final nanostructure patterns. This multi-step segmentation enables achieving higher patterning precision (below 10nm) that cannot be obtained through single-step lithography, thereby resolving the contradiction between increased integration density and maintained patterning precision.
2Quantity of substance
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but device performance and reliability become harder to maintain
Solution Approach 1:
The patent applies local quality by forming alternating semiconductor layers with different materials (e.g., first semiconductor material and second semiconductor material) that have distinct properties. These layers are selectively etched to create nanostructures with tailored local characteristics. Additionally, strain engineering is applied locally in the channel regions through selective epitaxial growth of source/drain structures, maintaining device performance and reliability even as feature sizes are reduced for higher integration density.
3Manufacturing precision
If double-patterning or multi-patterning techniques are used to achieve precise patterning, then nano-FETs with improved integration density can be fabricated, but the manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by first forming a mandrel layer with initial patterns before creating the final spacer structures. The mandrel layer serves as a template that guides subsequent spacer deposition and patterning. This preliminary structuring simplifies the overall multi-patterning process by providing a defined starting point, reducing the complexity that would otherwise arise from attempting to create complex patterns directly without intermediate guiding structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the efficient fabrication of nano-FETs with improved integration density and performance by ensuring precise patterning and strain engineering of semiconductor materials, thereby enhancing the operational efficiency of semiconductor devices.
Implementation Method 1
after the anneal process, a second p-metal work function layer is formed. In an embodiment, the base structure includes less than 50% oxygen by atomic weight prior to the anneal process and includes greater than 50% oxygen by atomic weight after the anneal process
Data Source
AI summary
Semiconductor devices and methods of manufacturing the semiconductor devices are disclosed herein. The methods include forming nanostructures in a multilayer stack of semiconductor materials. An interlayer dielectric is formed surrounding the nanostructures and a gate dielectric is formed surrounding the interlayer dielectric. A first work function layer is formed over the gate dielectric. Once the first work function layer has been formed, an annealing process is performed on the resulting structure and oxygen is diffused from the gate dielectric into the interlayer dielectric. After performing the annealing process, a second work function layer is formed adjacent the first work function layer. A gate electrode stack of a nano-FET device is formed over the nanostructures by depositing a conductive fill material over the second work function layer.