Stacked MBCFET Channel Structure for Short-Channel Leakage Control
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Solution Overview
Problem
As semiconductor devices are scaled down, the operating characteristics of metal oxide semiconductor field effect transistors (MOSFETs) deteriorate, leading to issues such as short channel effects, high current leakage, and increased sub-threshold swing, which affect the overall performance of the semiconductor device.
Innovation Solution
The semiconductor device incorporates a three-dimensional field effect transistor (MBCFET) design with stacked semiconductor patterns and a gate electrode that surrounds the channel patterns, featuring recess and protrusion structures to maintain channel length and reduce electric field strength, along with a gate dielectric layer that includes ferroelectric and paraelectric materials to enhance electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET sizes are scaled down to increase integration, then device density increases, but operating characteristics deteriorate with increased short channel effects and current leakage
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional vertically stacked channel patterns, allowing multiple channels to occupy the same footprint area. This dimensional change enables higher integration density while maintaining sufficient channel length in each stack to reduce short channel effects and improve transistor reliability.
Solution Approach 2:
The channel region is segmented into multiple discrete semiconductor patterns stacked vertically, with gate electrodes surrounding each stack. This segmentation allows independent optimization of each channel stack's electrical characteristics while achieving high overall integration, addressing both density and reliability requirements.
2Length of moving object
If channel length is reduced to shrink device size, then device dimensions decrease, but electric field strength increases causing higher leakage
Solution Approach 1:
The patent modifies the physical and material parameters of the channel structures, including using different semiconductor materials with varying effective masses and mobility characteristics. These parameter changes enable shorter physical dimensions while controlling electric field strength through material properties, reducing gate-induced drain leakage.
Solution Approach 2:
Gate electrodes are nested around the vertically stacked channel patterns in a surrounding configuration, creating multiple gating regions along the channel length. This nested arrangement provides enhanced electrostatic control over the channel, suppressing leakage currents even when individual channel segments are short.
3Reliability
If sub-threshold swing is reduced to improve switching characteristics, then transistor switching performance improves, but device complexity increases
Solution Approach 1:
The patent employs composite material structures including high-k dielectric gate insulators combined with metal gate electrodes, and vertically stacked semiconductor channels with different material compositions. These composite structures enable improved sub-threshold swing characteristics through enhanced electrostatic control and material-specific electrical properties, achieving better switching without excessive complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves electrical properties by reducing sub-threshold swing and gate-induced drain leakage, maintaining effective channel length, and enhancing transistor performance even at reduced device sizes.
Implementation Method 1
a gate dielectric layer that includes ferroelectric and paraelectric materials to enhance electrical properties
Implementation Method 2
a gate dielectric layer that includes ferroelectric and paraelectric materials to enhance electrical properties
Data Source
AI summary
A semiconductor device may include an active pattern on a substrate, a lower channel pattern on the active pattern and including first and second lower semiconductor patterns, an upper channel pattern on the lower channel pattern and including first and second upper semiconductor patterns, a pair of lower source/drain patterns on opposite sides of the lower channel pattern and a pair of upper source/drain patterns on opposite sides of the upper channel pattern, and a gate electrode surrounding the lower and upper channel patterns. The gate electrode may include a first upper portion between the first and second upper semiconductor patterns, and a first lower portion between the first and second lower semiconductor patterns. Each semiconductor pattern may include a first recess part having a first recess region on a top surface thereof, and a first protrusion part protruding from a bottom surface of the first recess part.