Semiconductor Gate Isolation Features for Overlay-Accurate Metal Gate Etch
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Solution Overview
Problem
Existing semiconductor fabrication methods, such as cut-poly-gate (CPO) and cut-metal-gate (CMG) processes, face issues with insufficient metal track placement and overlay errors during photolithography, leading to inaccurate cutting results, especially when processing gates with different critical dimensions.
Innovation Solution
A method involving the formation of isolation features using a series of photolithography and etching processes to create three-dimensional fins separated by dielectric materials, followed by the deposition of cladding and isolation structures, and the formation of dielectric helmets to improve gate isolation, allowing for better control of the metal gate etch process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If self-aligned CPO process is used, then alignment between gate and isolation features is improved, but metal track placement becomes insufficient
Solution Approach 1:
The process is divided into separate stages: first forming isolation features, then forming metal gate structures with their own alignment references. This segmentation allows each feature type to be optimized independently, preventing the trade-off where improving gate-isolation alignment degrades metal track placement.
2Manufacturing precision
If CMG process is used, then gate isolation is improved, but overlay errors occur during photolithography leading to inaccurate cutting results
Solution Approach 1:
Alignment markers are introduced as intermediary reference features that mediate between the photolithography patterning step and the final gate isolation formation. These markers provide a stable reference frame that decouples the overlay accuracy from the final cutting precision, allowing accurate gate isolation even when photolithography overlay has errors.
3Adaptability or versatility
If photolithography process is used for patterning, then fabrication flexibility is improved, but overlay errors lead to inaccurate cutting results
Solution Approach 1:
Alignment markers are formed in advance during the photolithography process, serving as pre-established reference features. This preliminary action allows subsequent etching and cutting operations to reference these pre-formed markers rather than relying on direct photolithography overlay, thereby maintaining fabrication flexibility while improving cutting accuracy.
4Productivity
If simultaneous processing of gates with different critical dimensions is performed, then production efficiency is improved, but processing accuracy decreases
Solution Approach 1:
The alignment marker system provides local reference frames that can be independently optimized for different gate regions with different critical dimensions. Each gate area can use the same photolithography process but reference local alignment markers tailored to its specific dimensional requirements, enabling simultaneous processing of diverse gates while maintaining high precision for each.
Data Source
AI summary
A method includes patterning a stack to form first and second semiconductor fins, forming first and second dielectric fins interleaved with the first and second semiconductor fins, forming a dummy gate stack over the first and second semiconductor fins and over the first and second dielectric fins, etching the dummy gate stack to form a first trench and a second trench, the first trench exposing a sidewall of the first dielectric fin, the second trench exposing a top surface of the second dielectric fin, depositing a first isolation feature in the first trench and a second isolation feature in the second trench, and removing the dummy gate stack to form a gate trench, removing the sacrificial layers from the gate trench, and depositing a metal gate stack in the gate trench, the metal gate stack wrapping around at least one of the channel layers.