Stacked Transistor Gate Electrode Deposition for Seam-Free Gap Fill
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating stacked transistors with seamless gate structures due to the introduction of complex geometric features as minimum feature sizes are reduced, leading to issues in gap filling and etch profile control, which affect device performance and processing ease.
Innovation Solution
A method involving chemical vapor deposition (CVD) and atomic layer deposition (ALD) is used to deposit work function metal (WFM) layers with controlled precursor sticking coefficients, employing a first precursor with a high sticking coefficient for upper surfaces and a second precursor with a low sticking coefficient for lower surfaces, followed by a reactant to form a seam-free gate electrode through a bottom-up deposition process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional deposition methods are used to fill gate gaps, then the deposition process is simple, but the gap filling is incomplete and produces seams in the gate electrode
Solution Approach 1:
The deposition process is segmented into multiple sequential deposition cycles, each depositing a portion of the gate electrode material. This allows complete filling of complex 3D gate structures without forming seams, as each cycle builds upon the previous one to progressively fill the gap
Solution Approach 2:
The deposition is performed through periodic cycles of depositing material layers, with each cycle consisting of specific deposition steps. This periodic action ensures uniform and complete gap filling while maintaining control over the deposition process to avoid seam formation
2Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated, but complex geometric features are introduced that worsen gap filling and etch profile control
Solution Approach 1:
The deposition process applies different deposition conditions and parameters to different regions of the gate structure. By controlling deposition locally within the complex 3D geometry, complete and uniform gap filling is achieved even in highly scaled devices with complex features
Solution Approach 2:
Deposition parameters such as temperature, pressure, and material flow rates are adjusted and optimized for each deposition cycle. These parameter changes enable precise control over the deposition process to achieve complete gap filling in scaled devices while maintaining manufacturing feasibility
3Reliability
If seam-free gate electrodes are achieved through multiple deposition cycles, then resistance is reduced and performance is enhanced, but the deposition process becomes more complex
Solution Approach 1:
The multiple deposition cycles are designed to continuously build upon each other, with each cycle contributing to the formation of a seamless gate electrode. This continuous action ensures complete gap filling and seam-free structure formation, achieving low resistance and high device performance
Solution Approach 2:
The deposition process is designed to be self-aligning and self-correcting through the sequential cycles. The process automatically ensures complete gap filling and seam-free formation without requiring additional intervention or complex post-processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves seamless gap filling in complex geometries, reducing resistance and improving etch profile control, resulting in enhanced device performance and processing ease.
Implementation Method 1
a first precursor is flowed into the opening, wherein the first precursor attaches to upper surfaces in the opening
Implementation Method 2
a second precursor is flowed into the opening, wherein the second precursor attaches to lower surfaces in the opening
Implementation Method 3
a reactant is flowed into the opening, wherein the reactant reacts with the second precursor
Implementation Method 4
chemical vapor deposition (CVD) and atomic layer deposition (ALD) is used to deposit work function metal (WFM) layers
Data Source
AI summary
A method of forming a semiconductor device includes depositing a target metal layer in an opening. Depositing the target metal layer comprises performing a plurality of deposition cycles. An initial deposition cycle of the plurality of deposition cycles comprises: flowing a first precursor in the opening, flowing a second precursor in the opening after flowing the first precursor, and flowing a reactant in the opening. The first precursor attaches to upper surfaces in the opening, and the second precursor attaches to remaining surfaces in the opening. The first precursor does not react with the second precursor, and the reactant reacts with the second precursor at a greater rate than the reactant reacts with the first precursor.