Extended Contact Structure for GAA FET Channel Control
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Solution Overview
Problem
Existing gate-all-around (GAA) FET devices face challenges in achieving full depletion of the channel region and controlling the current due to the unenclosed bottom side of the channel, leading to short-channel effects and increased contact resistance, which affect device performance and integration.
Innovation Solution
The method involves forming a multi-gate semiconductor structure with nanowires surrounded by a gate electrode, using a dummy gate structure to create recesses and fill them with semiconductor layers, followed by dielectric and metal silicide layers to enhance control over the channel region and reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a FinFET structure with gate adjacent to three side surfaces is used, then device density and performance are improved, but the bottom part of the channel region is not under close gate control leading to short-channel effects
Solution Approach 1:
The patent transitions from a planar FinFET structure to a three-dimensional gate-all-around (GAA) structure where the gate electrode completely surrounds the channel region including the bottom surface. This dimensional change enables full depletion of the channel and eliminates short-channel effects while maintaining high device density through vertical stacking of multiple nanowires.
Solution Approach 2:
The gate electrode is positioned to completely surround each nanowire channel region in a nested configuration, with the gate dielectric layer interposed between the gate electrode and the channel. This nested arrangement ensures that all surfaces of the channel including the bottom are under close gate control, achieving full depletion and eliminating short-channel effects.
2Ease of manufacture
If the channel region bottom is not enclosed by gate electrode, then fabrication is simpler, but contact resistance increases and device performance deteriorates
Solution Approach 1:
The gate electrode completely surrounds each nanowire channel region in a nested configuration, with the gate dielectric layer interposed between the gate electrode and the channel. This nested arrangement ensures that all surfaces of the channel including the bottom are under close gate control, achieving full depletion and eliminating short-channel effects.
3Reliability
If existing GAA FET devices are used, then full depletion of channel is achieved, but short-channel effects and contact resistance remain problematic
Solution Approach 1:
The channel region is segmented into multiple discrete nanowires instead of a single continuous channel. Each nanowire is independently surrounded by its own gate electrode, allowing for complete depletion of each nanowire channel. This segmentation eliminates short-channel effects while maintaining full depletion control, and the multiple nanowires can be stacked vertically to achieve high device density.
Data Source
AI summary
Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. In addition, the nanostructures includes channel regions and source/drain regions. The semiconductor structure further includes a gate structure vertically sandwiched the channel regions of the nanostructures and a contact wrapping around and vertically sandwiched between the source/drain regions of the nanostructures.