GAA FET Isolation Structure With Etch-Resistant Dielectric Layer
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Solution Overview
Problem
Isolation structures in gate-all-around field-effect transistors (GAA FETs) are vulnerable to dry etching and wet cleaning processes, leading to over-etching and excessive junction leakage.
Innovation Solution
The formation of isolation structures using silicon oxide deposited by flowable chemical vapor deposition (CVD) is enhanced by incorporating a carbon-doped dielectric layer that protects the isolation structure from subsequent etching processes, reducing junction leakage by maintaining the integrity of the isolation structure during fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If silicon oxide is deposited using flowable CVD to form isolation structures, then the isolation structures can be formed with good conformality and coverage, but the isolation structures become vulnerable to dry etching and wet cleaning processes, leading to over-etching and excessive junction leakage
Solution Approach 1:
The patent applies composite materials by forming a multi-layer isolation structure comprising a first dielectric layer (silicon oxide deposited by flowable CVD) and a second dielectric layer (different material composition) deposited thereover. This composite structure combines the conformal coverage benefits of flowable CVD silicon oxide with the etch resistance of the second dielectric material, resolving the contradiction between ease of manufacture and reliability by preventing over-etching while maintaining good coverage.
2Manufacturing precision
If dry etching and wet cleaning processes are used to form GAA FETs, then the transistor structures can be precisely formed, but the isolation structures are over-etched, leading to excessive junction leakage
Solution Approach 1:
The patent applies beforehand cushioning by depositing a second dielectric layer over the first dielectric layer (isolation structure) before the dry etching and wet cleaning processes. This protective layer acts as a cushion that prevents the isolation structure from being over-etched during subsequent processing steps, allowing precise GAA FET formation while maintaining isolation structure integrity and preventing junction leakage.
3Area of stationary object
If the isolation structure is made thinner to reduce device footprint, then the IC chip footprint is reduced, but the isolation structure becomes more susceptible to etching damage and junction leakage
Solution Approach 1:
The patent applies composite materials by creating a multi-layer isolation structure where a thin first dielectric layer provides the necessary isolation function with reduced footprint, while a second dielectric layer with different material composition provides enhanced etch resistance. This composite approach allows the isolation structure to be thinner (reducing chip footprint) while simultaneously being more resistant to etching damage (reducing vulnerability to harmful factors).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed method effectively mitigates junction leakage by ensuring the isolation structure remains intact, thereby improving the reliability and performance of GAA FETs.
Implementation Method 1
isolation structures (e.g., shallow trench isolation or STI) in GAA FETs may be formed with silicon oxide deposited using flowable chemical vapor deposition (CVD)
Implementation Method 2
incorporating a carbon-doped dielectric layer that protects the isolation structure from subsequent etching processes
Data Source
AI summary
A semiconductor device includes a substrate, a first fin-shaped structure protruding from the substrate, a second fin-shaped structure protruding from the substrate, an isolation structure disposed between the first fin-shaped structure and the second fin-shaped structure, a first epitaxial feature atop the first fin-shaped structure, a second epitaxial feature atop the second fin-shaped structure, an etch stop layer covering the first and second epitaxial features, and a dielectric structure. The isolation structure interfaces a sidewall of the first fin-shaped structure and a sidewall of the second fin-shaped structure. A top surface of the isolation structure is non-planar. The dielectric structure is vertically between the isolation structure and the etch stop layer and laterally between the etch stop layer and at least one of the first and second epitaxial features.