Multi-Gate Inner Spacer Structure With Air Gaps for Lower Capacitance
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Solution Overview
Problem
Existing inner spacer features in multi-gate transistors, such as MBC transistors, provide adequate etch resistance but increase parasitic capacitance due to high dielectric constant materials, degrading device performance.
Innovation Solution
Incorporating a dielectric layer and air gaps in the inner spacer features to reduce parasitic capacitance by using a combination of dielectric layers and voids or seams, which are formed during the deposition of spacer material layers, thereby reducing the dielectric constant in critical areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inner spacer features are formed of etch resistant dielectric material, then etch resistance is improved, but parasitic capacitance increases due to high dielectric constant
Solution Approach 1:
The inner spacer feature is formed as a composite structure comprising a first dielectric material layer (providing etch resistance) and a second dielectric material layer with air gaps (providing low dielectric constant). This composite approach combines the advantages of both materials to simultaneously achieve etch resistance and reduced parasitic capacitance.
Solution Approach 2:
The second dielectric material layer contains air gaps that create a porous structure with effectively reduced dielectric constant. The air gaps (voids) within the dielectric layer reduce the overall capacitance between the gate structure and source/drain features while maintaining the structural integrity needed for etch resistance.
2Object-generated harmful factors
If dielectric constant is reduced to lower parasitic capacitance, then device performance is improved, but etch resistance may be compromised
Solution Approach 1:
The inner spacer feature is segmented into two distinct dielectric material layers, each performing a specialized function. The first layer provides etch resistance while the second layer with air gaps provides low dielectric constant, allowing each segment to optimize its specific function without compromising the other.
Solution Approach 2:
Different regions of the inner spacer feature have different material properties tailored to local requirements. The region closer to the gate structure uses high etch resistance material, while the region closer to the source/drain features uses low dielectric constant material with air gaps, optimizing both etch protection and capacitance reduction locally.
Data Source
AI summary
A semiconductor device and a method of forming the same are provided. In an embodiment, an exemplary semiconductor device includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, and a source/drain feature disposed over the substrate and coupled to the vertical stack of channel members. The source/drain feature is spaced apart from a sidewall of the gate structure by an air gap and a dielectric layer, and the air gap extends into the source/drain feature.