Air Inner Spacer Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
The inner spacer structures in GAA finFET devices form parasitic capacitors that degrade device performance due to their lower etching selectivity and blockage, leading to parasitic capacitance and resistance issues.
Innovation Solution
Forming air inner spacers by removing a portion of the inner spacer structure between the S/D epitaxial and gate structures, using a second spacer layer with higher etch selectivity, and sealing the opening with a dielectric layer to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inner spacer structures are formed between gate and S/D structures, then structural support and isolation are provided, but parasitic capacitance increases and device performance degrades
Solution Approach 1:
The patent changes the dielectric parameter of the inner spacer by replacing traditional dielectric materials with air, which has a significantly lower dielectric constant (k≈1). This parameter change reduces the parasitic capacitance formed between the gate and S/D structures, directly addressing the harmful effect while maintaining the structural isolation function.
Solution Approach 2:
The patent introduces air voids (porous structure) within the inner spacer region by forming openings through the traditional dielectric material and filling with air. This porous configuration reduces the effective dielectric constant of the inner spacer, thereby reducing parasitic capacitance while maintaining mechanical support.
2Reliability
If air inner spacers are formed to reduce parasitic capacitance, then device performance improves, but manufacturing complexity increases due to additional etching and sealing steps
Solution Approach 1:
The patent performs preliminary actions by forming the air inner spacer structure early in the manufacturing process, before final device assembly. The openings are created and sealed with dielectric layers during intermediate processing steps, allowing the air gap structure to be established before subsequent manufacturing operations. This preliminary formation integrates the air spacer creation into the existing manufacturing flow rather than adding separate post-processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces parasitic capacitance by 5% to 10% and improves device performance by 5% to 10% by using air inner spacers with a lower dielectric constant.
Implementation Method 1
sealing the opening with a dielectric layer to reduce parasitic capacitance
Data Source
AI summary
The present disclosure describes a method to form a semiconductor device with air inner spacers. The method includes forming a semiconductor structure on a first side of a substrate. The semiconductor structure includes a fin structure having multiple semiconductor layers on the substrate, an epitaxial structure on the substrate and in contact with the multiple semiconductor layers, a gate structure wrapped around the multiple semiconductor layers, and an inner spacer structure between the gate structure and the epitaxial structure. The method further includes removing a portion of the substrate from a second side of the substrate to expose the epitaxial structure and the inner spacer structure, forming an oxide layer on the epitaxial structure on the second side of the substrate, and removing a portion of the inner spacer structure to form an opening. The second side is opposite to the first side of the substrate.