Multi-Gate GAA Transistor Layout for Leakage and Drive Current Tuning
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Solution Overview
Problem
Existing techniques have not satisfactorily addressed the challenge of providing multi-gate devices that meet diverse device performance requirements, particularly in terms of leakage current and drive current, complicating the fabrication process and increasing costs.
Innovation Solution
The formation of GAA transistors with varying numbers of channel layers and dielectric features to meet specific application requirements, such as low power consumption or high performance, by selectively forming dielectric features in different device regions to control leakage and drive currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate devices are introduced to improve gate control and reduce off-state current, then gate-channel coupling is improved and short-channel effects are reduced, but device complexity and fabrication difficulty increase
Solution Approach 1:
The channel region is divided into multiple segments with different numbers of channel layers (first plurality vs. second plurality) to create devices with different performance characteristics. This segmentation allows simultaneous fabrication of devices optimized for different applications (low leakage vs. high drive current) within the same integrated circuit.
Solution Approach 2:
Different regions of the channel are given different local properties by varying the number of channel layers in different device regions. The first device region has a first number of channel layers optimized for low off-state current, while the second device region has a second number of channel layers optimized for high drive current, allowing each region to have tailored performance.
2Adaptability or versatility
If diverse device performance requirements are met by creating different device types, then device performance is optimized for specific applications, but fabrication process complexity and costs increase
Solution Approach 1:
Multiple device types with different performance characteristics are merged into a single integrated circuit using a unified fabrication process. The method combines the formation of first devices with first plurality of channel layers and second devices with second plurality of channel layers in the same process flow, reducing fabrication steps and costs while maintaining performance differentiation.
Solution Approach 2:
The fabrication process is designed to be universal, capable of producing multiple device types (different channel layer configurations) simultaneously. The same epitaxial growth process and same fabrication steps are used to create both low-leakage devices and high-drive-current devices, making the process adaptable to diverse performance requirements without requiring separate manufacturing lines.
3Area of moving object
If channel layers are reduced to decrease device area, then area efficiency is improved, but drive current may be reduced
Solution Approach 1:
The number of channel layers is made dynamic and adjustable based on device region requirements. Instead of using a fixed number of channel layers throughout the substrate, the structure allows varying the channel layer count (first plurality vs. second plurality) to optimize the balance between area efficiency and drive current for different application needs within the same integrated circuit.
Data Source
AI summary
Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, a dielectric feature disposed directly on the substrate and in direct contact with a portion of the vertical stack of channel members, and a source/drain feature disposed directly on the dielectric feature and electrically coupled to a remaining portion of the vertical stack of channel members.