Strained Nanosheet Channels on SOI Without SiGe Buffer Layers
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Solution Overview
Problem
The use of a SiGe strain-relaxed buffer layer in semiconductor manufacturing degrades channel quality and limits performance due to restricted channel strain and crystal quality issues, and is also costly.
Innovation Solution
Replace the SiGe strain-relaxed buffer layer with a partially-strained or fully strain-relaxed Si/SiGe bi-layer on a modified silicon-on-insulator (SOI) structure, allowing for the growth of compressively strained SiGe channels for PMOS devices and tensile-strained silicon channels for NMOS devices, enhancing carrier mobility and transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a SiGe strain-relaxed buffer layer is used, then device fabrication is enabled, but channel quality degrades and performance is limited due to restricted channel strain and crystal quality issues
Solution Approach 1:
The patent removes the SiGe strain-relaxed buffer layer from the device structure entirely. By extracting this problematic layer, the invention eliminates the source of crystal quality issues and restricted strain, allowing direct growth of strained SiGe channels on relaxed SiGe layers without intermediate buffer constraints
Solution Approach 2:
The invention employs a composite structure consisting of multiple layers with different strain states: relaxed SiGe layers provide a stable foundation, while strained SiGe channels grown directly on them achieve superior crystal quality and enhanced carrier mobility through controlled strain without the limitations of traditional buffer layers
2Ease of manufacture
If a SiGe strain-relaxed buffer layer is used, then structural support is provided, but manufacturing costs increase
Solution Approach 1:
The patent eliminates the SiGe strain-relaxed buffer layer, which is identified as a costly component in traditional fabrication processes. This extraction reduces material usage and manufacturing complexity while maintaining structural integrity through the relaxed SiGe layer foundation
3Productivity
If channel dimensions are scaled down, then device density increases, but manufacturing complexity increases
Solution Approach 1:
The patent prepares the substrate surface in advance by forming relaxed SiGe layers with controlled composition and structure before growing the strained SiGe channels. This preliminary preparation ensures optimal growth conditions and simplifies subsequent fabrication steps, reducing overall manufacturing complexity despite scaled dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The modified SOI structure enables higher carrier mobility, improving switching speed and device performance while allowing for a wider range of germanium concentrations in SiGe films, reducing manufacturing complexity and costs.
Implementation Method 1
a strained semiconductor layer, such as silicon germanium (SiGe), is formed over a portion of the substrate in a channel region of a transistor
Implementation Method 2
the strained semiconductor layer is formed over a strain-relaxed layer, such as a silicon germanium (SiGe) layer
Data Source
AI summary
A strain-relaxed silicon/silicon germanium (Si/SiGe) bi-layer can be used as a foundation for constructing strained channel transistors in the form of nanosheet gate all-around field effect transistors (GAAFETs). The bi-layer can be formed using a modified silicon-on-insulator process. A superlattice can then be epitaxially grown on the bi-layer to provide either compressively strained SiGe channels for a p-type metal oxide semiconductor (PMOS) device, or tensile-strained silicon channels for an n-type metal oxide semiconductor (NMOS) device. Composition and strain of the bi-layer can influence performance of the strained channel devices.