Active-Degeneration DAC Circuit for Low-Flicker PLL Tuning
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Solution Overview
Problem
Existing digital-to-analog converters (DACs) in phase locked loops (PLLs) operating at millimeter-wave frequencies face challenges in meeting stringent integrated phase noise specifications and wide frequency tuning range requirements, particularly due to high flicker noise and large area consumption.
Innovation Solution
Implementing active degeneration in the DAC circuit using non-DAC transistor devices to provide adjustable degenerative resistance, controlled by a feedback signal, which reduces low-frequency 1/f noise and maintains a wide current output range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of bits for high-order signal lines is increased to improve resolution, then manufacturing precision and cost increase, but device complexity and manufacturing difficulty worsen
Solution Approach 1:
The digital-to-analog converter is divided into multiple independent conversion units, each handling a subset of signal lines. This segmentation allows each unit to use fewer bits per signal line while maintaining overall high resolution through parallel processing, thereby reducing manufacturing precision requirements and device complexity.
Solution Approach 2:
The patent transitions from a single-dimensional approach (increasing bits per line) to a multi-dimensional approach by introducing parallel conversion units. This dimensional change allows the system to achieve high resolution through spatial parallelism rather than increasing the complexity of individual signal paths.
2Measurement precision
If the number of bits for high-order signal lines is increased to improve resolution, then manufacturing precision and cost increase, but manufacturing precision worsens
Solution Approach 1:
By segmenting the converter into multiple units with fewer bits each, the manufacturing precision requirements for individual components are reduced. Each unit can be manufactured with standard precision tolerances while the parallel configuration maintains overall high resolution performance.
3Device complexity
If conventional digital-to-analog conversion methods are used, then device complexity increases, but productivity and ease of manufacture worsen
Solution Approach 1:
The segmented architecture with standardized conversion units enables modular manufacturing and assembly, improving productivity by allowing parallel production of identical modules that can be easily integrated, thereby reducing overall device complexity and easing manufacture.
4Object-affected harmful factors
If high-order signal lines use more bits to reduce noise, then device complexity increases, but ease of operation worsens
Solution Approach 1:
Segmenting the signal processing into multiple parallel units with fewer bits each reduces the complexity of individual signal paths while maintaining low noise performance through the combined output of all units, thereby easing device operation.
Data Source
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AI summary
A digital to analog converter (DAC) includes a plurality of DAC transistor devices having an input side configured to be selectively coupled to a system voltage based on a digital input signal and an output side configured to provide an analog output signal, a plurality of non-DAC transistor devices coupled to the input side of the DAC transistor devices, the non-DAC transistor devices configured as variable resistances, and a control circuit configured to adjust a bias of the non-DAC transistor devices.