Active Fin Insulation Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
Conventional semiconductor devices face challenges in reducing parasitic capacitance and leakage current due to the placement of dummy gates between multi-channel active fins, which affects the operating characteristics and efficiency of the devices.
Innovation Solution
The semiconductor device incorporates a field insulation layer with protruding portions that separate multi-channel active fins, allowing a conductive layer to cross over these protrusions, thereby reducing the contact area between dummy gates and active fins, which minimizes parasitic capacitance and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy gates are placed between multi-channel active fins, then device structure is formed, but parasitic capacitance and leakage current increase
Solution Approach 1:
The harmful dummy gate structure is completely removed from between the active fins. Instead, a conductive layer is formed that selectively contacts only the active fins while leaving gaps between them, extracting the harmful capacitance-generating element while preserving the beneficial gate function.
Solution Approach 2:
A dielectric layer is introduced as an intermediary between the conductive layer and the active fins, and between adjacent conductive layers. This mediator reduces parasitic capacitance by providing electrical isolation while still allowing the gate to control the active fins effectively.
2Reliability
If dummy gates are placed between multi-channel active fins, then device structure is formed, but leakage current increases
Solution Approach 1:
The dummy gate structure that causes leakage current is completely removed. The conductive layer is designed to make selective contact only with active fins through openings in the dielectric layer, eliminating the leakage paths that would exist with continuous dummy gates between fins.
Solution Approach 2:
The dielectric layer serves as an intermediary that blocks leakage current paths between adjacent active fins while still permitting controlled current flow through the gate when needed for device operation.
3Object-generated harmful factors
If conductive layer contacts active fins through dielectric layer, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The dielectric layer is formed between the conductive layer and active fins during the manufacturing process before final device assembly. This preliminary action of inserting the dielectric mediator during fabrication simplifies the overall process compared to attempting to add it later, and reduces parasitic capacitance in the finished device.
Data Source
AI summary
A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.