Active Matrix Array Structure Reducing Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The conventional active matrix array structure for liquid crystal display panels requires multiple photomasking processes, increasing manufacturing costs and complexity, while also facing challenges in maximizing display aperture ratio due to parasitic capacitors between pixel electrodes and data lines.
Innovation Solution
The active matrix array structure is fabricated using three photomasking processes, incorporating a patterned overcoat layer with recessed sidewalls to reduce parasitic capacitors and enhance display aperture ratio, with a transparent conductive layer partially overlapping data lines to increase display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If five photomasking processes are used to form a patterned overcoat layer, then the display aperture ratio is improved and parasitic capacitors are reduced, but the manufacturing cost increases
Solution Approach 1:
The patent combines multiple photomasking processes into fewer steps by using a single photomasking process to form both the pixel electrode pattern and the patterned overcoat layer. This merging of operations reduces the total number of photomasks from five to three, lowering manufacturing cost while maintaining the aperture ratio benefits of the patterned overcoat structure.
Solution Approach 2:
The overcoat layer is designed to serve multiple functions: it acts as an etching mask during fabrication, provides planarization for subsequent processing, and when patterned, reduces parasitic capacitance between the pixel electrode and data line. This multi-functionality allows a single structural element to address multiple design requirements without proportionally increasing complexity.
2Area of stationary object
If a patterned overcoat layer is formed to increase display aperture ratio, then the pixel electrode can cover more area, but the manufacturing process complexity increases
Solution Approach 1:
The patent merges the formation of the pixel electrode pattern and the patterned overcoat layer into a single photomasking step. The photomask is designed to simultaneously define both features, eliminating the need for separate photomasking processes and reducing overall process complexity despite the sophisticated final structure.
Solution Approach 2:
The overcoat layer is formed and patterned in advance before the pixel electrode is deposited. This preliminary action allows the overcoat to serve as a fabrication mask that simplifies subsequent processing steps, as the pixel electrode can be deposited directly without requiring additional masking operations to achieve the desired pattern.
3Area of stationary object
If the overcoat layer thickness is increased to reduce parasitic capacitors, then the pixel electrode coverage is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The overcoat layer is patterned with varying thickness in different regions: it is thicker in areas where parasitic capacitance reduction is critical (near data lines) and can be thinner or absent in other areas. This local variation in thickness allows optimization of electrical performance without uniformly increasing the precision requirements across the entire structure.
Solution Approach 2:
The patent utilizes photomask design and exposure parameters to control the overcoat layer thickness and pattern during a single photomasking process. By adjusting optical parameters and mask geometry rather than relying solely on physical deposition thickness control, the process achieves the required precision through parameter optimization rather than mechanical precision alone.
Data Source
AI summary
An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer.