Active Matrix Substrate Double Gate Wiring Notches
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The active matrix substrates disclosed in existing technologies, such as JP 2018-36315 A, face an issue with increased parasitic capacitance due to the overlap between shield wiring lines and scanning lines, which affects the performance of the display devices.
Innovation Solution
The proposed active matrix substrate incorporates an oxide semiconductor TFT with a double gate structure, featuring a lower gate electrode and an upper gate electrode, where the gate wiring lines are designed with notched portions and overlapping portions to reduce parasitic capacitance while maintaining the integrity of the gate wiring lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a shield wiring line is disposed on the substrate side of a semiconductor layer to form a double gate structure, then the TFT can operate at higher speed and the structure provides shielding, but parasitic capacitance increases due to overlap between the shield wiring line and scanning line
Solution Approach 1:
The lower gate wiring line is divided into multiple segments by introducing notched portions that remove conductive material. This segmentation reduces the overlapping area between the lower gate wiring line and upper gate wiring line, thereby reducing parasitic capacitance while maintaining the double gate structure's shielding and high-speed operation capabilities
Solution Approach 2:
The notched portions are strategically positioned at specific locations where the lower gate wiring line overlaps with upper gate wiring lines. This local modification reduces parasitic capacitance at critical overlap regions while preserving the overall double gate structure and its functional benefits in other areas
2Object-generated harmful factors
If gate wiring lines are designed with notched portions to reduce parasitic capacitance, then parasitic capacitance is reduced, but the structural integrity of the gate wiring lines may be compromised
Solution Approach 1:
The notched portions are designed and positioned in advance during the wiring line formation process. By pre-planning the notch locations and dimensions, the structure maintains sufficient conductive material in critical areas to ensure mechanical strength and electrical connectivity while achieving parasitic capacitance reduction
Solution Approach 2:
The notched portions remove only a partial amount of conductive material - enough to reduce parasitic capacitance to acceptable levels but not so much as to compromise the structural integrity or electrical performance of the gate wiring lines. The remaining conductive material maintains sufficient strength and conductivity
Data Source
AI summary
An active matrix substrate includes a substrate, a plurality of oxide semiconductor TFTs each including an oxide semiconductor layer, a lower gate electrode positioned on the substrate side of the oxide semiconductor layer, and an upper gate electrode positioned on the oxide semiconductor layer on a side opposite from the substrate, a plurality of source wiring lines extending in a column direction, a plurality of upper gate wiring lines extending in a row direction, and a plurality of lower gate wiring lines extending in the row direction. The plurality of lower gate wiring lines include a first gate wiring line, and the plurality of upper gate wiring lines include a second gate wiring line partially overlapping the first gate wiring line via the lower gate insulating layer and the upper gate insulating layer. The plurality of oxide semiconductor TFTs include a first TFT including an oxide semiconductor layer extending across the first gate wiring line and the second gate wiring line in the column direction, when viewed from a normal direction of the substrate. Portions of the first gate wiring line and the second gate wiring line, over which the oxide semiconductor layer of the first TFT extends, respectively function as the lower gate electrode and the upper gate electrode of the first TFT. When viewed from the normal direction of the substrate, the first gate wiring line includes a plurality of first notched portions disposed spaced apart from each other and a first solid portion, the first solid portion being a portion other than the plurality of first notch portions. When viewed from the normal direction of the substrate, the second gate wiring line includes a second solid portion including a plurality of first overlapping portions disposed spaced apart from each other, each of the first overlapping portions partially overlapping at least one of the plurality of first notched portions, and a second overlapping portion overlapping the first solid portion. When viewed from the normal direction of the substrate, the second overlapping portion continuously extends from one of two of the plurality of source wiring lines adjacent to each other, to the other of the two source wiring lines adjacent to each other.