Three-Layer Active Pillars for 1T0C DRAM Charge Retention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor structures, such as 1T1C DRAMs, occupy a large area and have a low space utilization rate, while 1T0C DRAMs face challenges in practical implementation of the float body effect for charge storage.
Innovation Solution
A semiconductor device with active pillars comprising three semiconductor layers, each corresponding to a respective word line, forming a 1T0C architecture with a front gate for switching and a back gate for charge storage, utilizing a quantum well to accumulate excess holes and reduce junction leakage, thereby increasing integration and data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If 1T1C DRAM structure is used, then data storage capability is provided, but area occupation increases and space utilization rate decreases
Solution Approach 1:
The patent removes the capacitor component from the traditional 1T1C structure, extracting the charge storage function and relocating it to the transistor body through the quantum well formed by the heterojunction. This eliminates the need for separate capacitor structures, thereby reducing area occupation while maintaining data storage capability.
Solution Approach 2:
The patent merges the charge storage function (previously separate capacitor) with the transistor body by forming a quantum well within the transistor structure. The heterojunction creates potential wells that trap carriers directly in the transistor body, combining switching and storage functions into a single integrated structure.
2Area of stationary object
If 1T0C DRAM structure is used to reduce area, then space utilization improves, but implementation of float body effect for charge storage becomes challenging
Solution Approach 1:
The patent changes the material composition parameters by introducing a heterojunction with different band gaps. The second semiconductor layer has a smaller band gap than the first and third layers, creating a quantum well that changes the energy parameters for carrier confinement. This enables effective charge storage in the transistor body without requiring a separate capacitor.
Solution Approach 2:
The patent employs composite semiconductor materials forming a heterojunction structure. The active pillar includes first, second, and third semiconductor layers with different material compositions and band gap characteristics. This composite structure creates the quantum well effect necessary for charge storage in the 1T0C configuration.
3Productivity
If active pillars extend in first direction parallel to substrate plane, then integration level increases, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from vertical transistor structures to horizontal active pillars that extend in the first direction parallel to the substrate plane. This dimensional change allows multiple active pillars to be arranged in arrays, increasing integration density. The word lines extend in the third direction to contact different layers of the stacked semiconductor structure, enabling three-dimensional integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances space utilization and integration level while reducing junction leakage and increasing data retention time by employing a 1T0C architecture with a heterojunction and quantum well for charge storage.
Implementation Method 1
utilizing a quantum well to accumulate excess holes and reduce junction leakage
Implementation Method 2
Each of the plurality of active pillars includes a first semiconductor layer, a second semiconductor layer and a third semiconductor layer stacked sequentially in the second direction
Data Source
AI summary
A semiconductor device, including: a substrate; an active pillar array structure located on the substrate; and a plurality of first word lines and a plurality of second word lines. The active pillar array structure includes a plurality of active pillars arrayed in a second direction and a third direction, each active pillar extends in a first direction. The active pillar includes a first semiconductor layer, a second semiconductor layer and a third semiconductor layer stacked sequentially in the second direction. The first word lines and the second word lines extend in the third direction. Each active pillar arranged in the third direction corresponds to a respective first word line and a respective second word line. Each first word line covers the first semiconductor layer in the respective active pillar, and each second word line covers the third semiconductor layer in the respective active pillar.