Active and Shadow Latch Transposition for Reduced Die Area

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Solution Overview

Problem

Existing hardware techniques for transposing matrices in a streaming context require a large array of hardware elements, consuming substantial die area and limiting throughput and processing speed.

Innovation Solution

Utilizing an array of active and shadow latches, where data is written to active latches and replicated in shadow latches, allowing for streaming transposition without increasing die area by separately controlling the latches with different clock gates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a large array of hardware elements is used to transpose matrices in a streaming context, then transposition capability is achieved, but die area consumption increases substantially

Engineering Contradiction:
Improvetransposition capabilityVSAvoiddie area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent divides the transposition hardware into two separate latch arrays: active latches for writing incoming data and shadow latches for storing transposed data. This segmentation allows the system to achieve matrix transposition capability while using only N latches instead of requiring a large N×N hardware array, thereby resolving the contradiction between transposition capability and die area consumption.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a two-dimensional N×N hardware array approach to a one-dimensional arrangement of N active latches and N shadow latches. By changing the dimensional organization of the hardware elements and using time-multiplexed operations, the system achieves the same transposition function with significantly reduced die area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If hardware elements are reduced to minimize die area, then die area efficiency improves, but throughput and processing speed may be limited

Engineering Contradiction:
Improvedie area efficiencyVSAvoidthroughput and processing speed
Core Design Contradiction:
Area of stationary objectVSProductivity

Solution Approach 1:

The patent employs periodic clock gating signals (first clock gate signal for active latches, second clock gate signal for shadow latches) to control data flow between latches and to output circuits. This periodic action enables pipelined operation where data can be continuously written to active latches and read from shadow latches in an alternating fashion, maintaining high throughput while using minimal hardware elements.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent achieves continuous data processing by maintaining both active and shadow latches in operational states simultaneously. While one latch array is being written to, the other is being read from, ensuring that the useful action of data transposition continues without interruption, thereby preserving throughput and processing speed despite reduced hardware.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS20250231742A1Transposing information using shadow latches and active latches for efficient die area in processing system
Publication Date: 2025.07.17 TESLA INC
  • US20250231742A1 patent drawing
  • US20250231742A1 patent drawing
  • US20250231742A1 patent drawing

AI summary

Systems and methods for transposing information using shadow latches and active latches for efficient die area in processing system. An example storage includes groups of active latches and shadow latches, with the active/shadow storage receiving a first matrix comprising values, and with the active latches being enabled, over first clock cycles, such that the values are stored in the active latches. The shadow latches replicate the values stored in the active latches. The values replicated in the shadow latches are read over second clock cycles, with at least one value included in a second matrix being stored in at least one active latch over second clock cycles.