Handling Data According To Predetermined Rules TRIZ Cases
- Neural Processor Data Reshaping for Non-Power-of-Two Work Units
A data processor reshapes non-power-of-two source data into power-of-two work units, helping neural engines improve utilization and reduce power consumption.
- Transformer Attention Weight Merging for Lower Memory Access
This case merges QK and VO weights before inference to reduce attention operations, memory access, and resource use on constrained devices.
- Cryptographic Group-Order Padding Against Low-Value Key Attacks
This cryptographic method uses group-order padding and Euclidean division to resist profiled side-channel attacks.
- Parallel Memory-Block Matrix Transposition for 3D FFTs
Multiple processing circuits use segmented memory regions for stall-free matrix transposition and faster multidimensional FFTs.
- DNN Weight Vector Rearrangement to Balance PE Sparsity
This DNN accelerator rearranges weight vectors with bitmaps to distribute sparse workloads across PEs and accelerate MAC operations.
- Active and Shadow Latch Transposition for Reduced Die Area
Separate clock-gated active and shadow latches support streaming matrix transposition with pipelined throughput and reduced die area.
- Vector Bitwise Rotations Using Shared Byte-Wise Mux Logic
This case combines a byte-wise mux with bitwise shifts to deliver vector rotations without dedicated logic for each element size.
- Sparse Weight Matrix Layout for Lower Inference Memory Usage
This case stores non-zero weights and positions after matrix reordering, reducing memory while limiting inference circuit scale.
- Matrix Transposition Masking Against Quantum and Side-Channel Attacks
This case uses shifted vectors, XOR combinations, and masking to protect matrix transposition from brute-force and side-channel attacks.