Parallel Memory-Block Matrix Transposition for 3D FFTs

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Solution Overview

Problem

Existing matrix transpose operations in large-scale fast Fourier transforms are rate limiting and adversely impact parallel processing due to memory access bottlenecks, particularly in 3D FFTs, leading to inefficiencies in integrated circuits like FPGAs.

Innovation Solution

Utilizing multiple processing circuits to concurrently write and read matrix elements in parallel across segmented memory blocks, leveraging abundant local memory bandwidth to perform transpose operations without replication, thereby reducing processing time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional matrix transpose operations are used in large-scale FFTs, then the transpose operation can be performed, but it becomes rate limiting and adversely impacts parallel processing due to memory access bottlenecks

Engineering Contradiction:

Improvetranspose operation speedVSAvoidprocessing time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The memory block is segmented into multiple regions that can be accessed in parallel by different processing circuits. Each processing circuit operates on different segments of the matrix simultaneously, dividing the transpose operation into parallel tasks that eliminate the memory access bottleneck and improve overall throughput.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a temporal dimension to the memory access pattern by having multiple processing circuits read from and write to different memory locations simultaneously. This transforms a sequential operation into a parallel operation, effectively adding a time dimension to the data processing workflow.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If multiple processing circuits are used to perform transpose operations in parallel, then processing time is reduced, but device complexity increases

Engineering Contradiction:

Improvetranspose operation throughputVSAvoidnumber of processing circuits

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The processing circuits are designed to perform multiple functions: they can read from memory blocks, write to memory blocks, and operate on different segments of the matrix. This multi-functionality allows the same circuit architecture to handle various tasks in the FFT pipeline, reducing the need for specialized hardware for each function.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines reading and writing operations into unified processing circuits that can perform both tasks. Instead of having separate read-only and write-only circuits, the design merges these functions into single circuits that can operate in different modes, thereby reducing the total number of circuits needed while maintaining parallel processing capability.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS12373170B2Techniques for transposing a matrix using a memory block

Publication Date: 2025.07.29 ALTERA CORP

AI summary

A circuit system includes a memory block and first and second processing circuits. The first and second processing circuits store a matrix in the memory block by concurrently writing first and second rows or columns of the matrix to first and second regions of storage in the memory block, respectively. The first and second processing circuits transpose the matrix to generate a transposed matrix by concurrently reading first and second rows or columns of the transposed matrix from third and fourth regions of storage in the memory block, respectively.