Active Tiling Placement for Latch-Up Immunity in CMOS SoC
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Solution Overview
Problem
CMOS structures face increased latch-up issues as device and circuit dimensions shrink, leading to potential destructive high current conduction states, which conventional methods struggle to address effectively, especially in System on Chip (SoC) designs where internal blocks prioritize density over latch-up risk.
Innovation Solution
The implementation of active tiles placed between circuit areas and tied to a reference supply or ground voltage, converted from dummy tiles, to enhance latch-up immunity, combined with a modified tile placement algorithm to ensure both chemical mechanical polishing uniformity and latch-up protection, by forming well regions with predetermined impurities and connecting them to appropriate supply voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device and circuit dimensions are scaled down, then productivity and integration density are improved, but latch-up immunity deteriorates
Solution Approach 1:
The chip area is divided into multiple tiles with isolation regions between them, creating segmented functional blocks. This segmentation limits the propagation of latch-up currents to local areas and allows independent control of each tile's electrical characteristics
Solution Approach 2:
Different regions of the chip are assigned different electrical characteristics through selective well tie connections. Tiles adjacent to high-risk circuit areas (I/O blocks, memory) are connected to reference voltages to create locally optimized latch-up protection zones without affecting the entire chip
2Reliability
If conventional latch-up protection methods are applied, then latch-up immunity is improved, but device area increases
Solution Approach 1:
The tile structure serves multiple functions simultaneously: it provides latch-up protection through well tie connections, maintains CMP uniformity through regular geometric patterns, and enables modular design for easy integration. This multi-functionality eliminates the need for separate protection structures that would consume additional area
Solution Approach 2:
Latch-up protection structures are merged with the regular tile and isolation region architecture. The well tie regions are integrated into the tile structure itself rather than being added as separate elements, and the isolation regions serve both electrical isolation and structural organization functions
3Manufacturing precision
If dummy tiles are placed for CMP uniformity, then manufacturing precision is improved, but latch-up protection is insufficient
Solution Approach 1:
The electrical parameters of the tile structures are modified by connecting certain tiles to reference supply voltages through well tie regions. This transforms ordinary dummy tiles into active protection elements that maintain both CMP uniformity (through their physical presence) and latch-up immunity (through their electrical connection to reference potentials)
Data Source
AI summary
A semiconductor device includes CMP dummy tiles (36) that are converted to active tiles by forming well regions (42) at a top surface of the dummy tiles, forming silicide (52) on top of the well regions, and forming a metal interconnect structure (72, 82) in contact with the silicided well tie regions for electrically connecting the dummy tiles to a predetermined supply voltage to provide latch-up protection.