A-D Comparator Buffer Equalization for Kickback Noise Control
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Solution Overview
Problem
Comparators with A-D converters face kickback noise issues during transitions from latch to reset conditions, which can lead to mistaken values at high sampling rates due to differing parasitic capacitances in positive and negative buffers, causing noise to be supplied back to the differential amplifier.
Innovation Solution
Incorporating a potential control section that sets the output ends of both positive and negative buffers to the same potential before the latch period ends, ensuring identical parasitic capacitances and reducing differential mode noise during transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the sampling rate of the A-D converter is increased to achieve high-speed operation, then productivity is improved, but kickback noise becomes more significant causing measurement errors
Solution Approach 1:
The potential control section performs preliminary action by equalizing the potentials of the positive and negative buffer output ends before the latch period ends. This preemptive equalization ensures that parasitic capacitances are balanced before transition begins, preventing kickback noise generation during the critical transition phase while maintaining high sampling rates.
2Productivity
If the comparator transitions quickly from latch to reset condition to maintain high sampling rate, then productivity is improved, but kickback noise is generated due to parasitic capacitance fluctuations
Solution Approach 1:
The potential control section executes preliminary action by equalizing buffer output potentials before the latch period concludes. This advance preparation balances parasitic capacitances prior to transition, enabling rapid switching without generating kickback noise from capacitance fluctuations during the transition itself.
Solution Approach 2:
The potential control section applies preliminary anti-action by counteracting the potential difference between positive and negative buffers before transition occurs. By equalizing potentials in advance, the system prevents the harmful capacitance fluctuations that would otherwise generate kickback noise during the necessary rapid transition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes kickback noise, allowing for accurate logic value acquisition even at high-speed operations by synchronizing the potential control between the buffers, thus reducing errors caused by parasitic capacitance fluctuations.
Implementation Method 1
Because the positive buffer 320 and the negative buffer 330 include transistors at an input side, the positive buffer 320 and the negative buffer 330 have a parasitic capacitance that relies on a bias voltage.
Data Source
AI summary
A comparator is provided that outputs a comparison result obtained by comparing two signals. The comparator includes a positive buffer that converts a positive comparison signal, which has a level according to a difference between the two signals, into a positive logic signal that indicates a logic level; a negative buffer that converts a negative comparison signal, which has a level that is inverted in relation to the positive comparison signal, into a negative logic signal that indicates a logic level that is inverted in relation to the positive logic signal; a latch core that, at a timing at which a latch period in which the comparison result is held begins, acquires the logic level of the positive logic signal and the logic level of the negative logic signal and holds the acquired logic levels; and a potential control section that, prior to a timing at which the latch period ends, sets an output end of the positive buffer to have a potential that is identical to that of an output end of the negative buffer.