Multiple Input And Output Pulse Circuits TRIZ Cases

Back-gate voltage control lets a display decoder widen output range and tune transistor threshold without extra masks or process steps.

Detects converter reading mode from terminal voltage to self-adapt current sensing, cutting noise and improving reading accuracy.

A delayed power input aligns comparator drive with PWM startup to prevent high-voltage overshoot and protect image-forming components.

A translinear buffer detector rectifies small differential signals while rejecting large common-mode noise with low current draw.

A current-mirror auxiliary path speeds reference voltage rise and sustains low-voltage detection during supply drops to prevent microcomputer faults.

Feedback-linearized transconductance and variable resistor ratios let one circuit deliver mixer and programmable gain functions with lower power and die size.

A module-integrated monitor sends activity, temperature, and voltage data to an external display, saving board space and cost.

A bipolar transistor and current mirror stabilize reference voltage against supply and temperature drift, improving receiver sensitivity and data judgment.

A dual-comparator sensing scheme cancels offset voltage for accurate zero-current turn-off in SMPS without extra pins or isolated PNPs.

A comparator, resistor divider, and multiplexer track internal supply voltage despite process and temperature variation for stable circuit operation.

Dynamic threshold adjustment in a high-speed DFE receiver adds voltage margin for transition bits to cut bit errors from jitter and ISI.

Separate low-pass filtering of clock rising and falling edges blocks high-speed leakage, preserves duty cycle, and cuts oscillator power.

A transition-only current discharge path keeps LVDS output slew rates symmetric at 1.8V, improving signal integrity without extra static current.

LPF outputs and comparator feedback preserve duty cycle information in divided high-frequency clocks, enabling accurate on-chip correction.

Reference and local delay blocks compare enable timing order to detect on-chip skew and support setup/hold time compensation.

Equal-sized FET legs and cross-coupled offset circuits enable accurate above-rail threshold detection without draining current from the input source.

Using differential clock signals to generate reference voltage internally removes extra pads and stabilizes signal reception and timing.

Switched load elements calibrate comparator input offset during production, improving stability without extra reference voltages or control signals.

Shared delay lines let a memory-interface DLL measure and generate delay accurately, cutting circuit scale, power use, and update faults.

By monitoring only the highest and lowest load voltages, this circuit cuts abnormal-voltage protection size and cost for multi-load modules.

Dual-threshold inverters and a filtered clock signal distinguish active and sleep modes while avoiding power-hungry frequency monitoring.

Variable positive feedback and mirrored load current give this comparator smooth sensitivity adaptation and controlled hysteresis at low supply voltage.

Comparator, gate, and multiplexer logic lets two LVDS devices share one differential pair for simultaneous communication with lower interconnect count.

A feedback phase correction circuit uses a replication output buffer and phase detector to cut multiphase clock skew and protect timing margin.

Comparator-controlled current mirrors preserve output amplitude, slew rate, and dynamic range in low-voltage signal output circuits.

A shared PMOS/NMOS output stage switches between small-amplitude standards while cutting chip area and leakage current.

A differential amplifier plus source follower extends rail-to-rail input while cutting circuit area and current consumption.

Feedback-controlled random clock generation spreads switching frequency to cut EMI while preserving triangular-wave linearity and audio fidelity.

Preset gate voltages and capacitive coupling let a CMOS level shifter amplify low-amplitude signals despite threshold variation and lower EMI noise.

Using intersecting V-to-I converters and current comparison, this case defines a repeatable low-voltage shutdown threshold even at very low current.

Feedback ends the drive pulse as soon as the output transition completes, preserving SRAM signal reliability without longer cycle time.

A feedback-driven reference voltage tracks bit line drop to speed read-0 sensing and reduce PVT sensitivity in large memory arrays.

Adjustable charge and discharge currents help an infrared receiver preserve error prevention while matching short input pulse periods.

A capacitor-based tracking circuit reconstructs supply-noise at the output transistor gate to preserve high-frequency data transmission speed.

Parallel current paths and a Wilson current mirror shut off steady-state current after switching, cutting power use and extending battery life.

A shared differential amplifier and switching circuit detects LVDS data bits with fewer comparators, cutting chip area and power.

Internal test circuits, a comparator, and a tuning unit let an IC rapidly correct process and temperature drift during operation.

Two controlled current sources and one capacitor compare PWM duty cycles without regulated supply voltage, cutting motor controller parts and cost.

Phase-shifted ramp voltages let one circuit generate dual PWM waves with accurate duty ratios and wider dynamic range at low supply voltages.

Differential offset compensation transistors calibrate dc-input offset, preserving comparator speed without larger transistors, extra power, or area.

Direct eye-pattern characterization at the flip-flop input calibrates sampling threshold and clock phase to cut data recovery errors.

Maintaining IO ports at high impedance during standby blocks bus noise and false signals, cutting current leakage and power use.

Dual bias comparators and hysteresis logic prevent oscillation near supply thresholds, reducing power dissipation and wrong rail selection.

Software-controlled multiplexer inputs let one comparator switch among signals and references, supporting low-power operation and capacitive sensing.

Timed level detection and latching identify floating, high, and low input states while reducing leakage current and noise interference.

A looped shift register tracks OR and AND clock results to catch clock tree desynchronization before injected faults corrupt logic.

A third NMOS path raises the second-node voltage under low input levels, cutting output delay and skew when supply voltage drops.

Phase-shifted clock sampling measures output skew on chip, replacing costly external ATE and improving multi-site test precision.

Equalizing positive and negative buffer outputs before reset suppresses kickback noise and preserves comparator accuracy at high sampling rates.

Bias-current-tracked source and sink currents keep comparator hysteresis voltage stable despite temperature and supply variations.