Passive Clock Detection Using Dual-Threshold Inverters
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Solution Overview
Problem
Conventional clock signal detection systems face challenges in accurately distinguishing between active and sleep modes with minimal power consumption, as they often rely on active monitoring of clock signal frequencies, which can be inefficient.
Innovation Solution
A passive clock detection apparatus comprising a low pass filter, low and high threshold inverters, a delay circuit, a latch, and logic to generate a clock detection signal, utilizing PMOS and NMOS FETs with specific aspect ratios to differentiate between active and sleep modes without substantial power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If active monitoring of clock signal frequencies is used to determine system modes, then detection accuracy is improved, but power consumption increases
Solution Approach 1:
The clock detector circuit uses the clock signal itself to drive the operation of the detector without requiring external power. The clock signal charges and discharges the capacitor, automatically generating voltage levels that trigger the inverters and logic gates, enabling mode detection with minimal power consumption from the VDD supply.
Solution Approach 2:
The circuit detects clock frequency by monitoring voltage level changes across a capacitor caused by the clock signal's charging and discharging cycles. The voltage threshold parameters of the inverters are specifically chosen to respond to these dynamic voltage changes, converting frequency information into detectable logic level transitions.
2Loss of energy
If clock signal frequency is reduced to DC in sleep mode, then power savings are achieved, but detection capability is lost
Solution Approach 1:
The capacitor acts as an intermediary element that accumulates charge from the clock signal and transforms it into a voltage level that can be detected by the logic circuit. This intermediary mechanism allows the detector to sense the presence or absence of clock activity even when the clock frequency is reduced to DC levels during sleep mode.
Solution Approach 2:
The circuit detects clock presence by monitoring the oscillating voltage levels across the capacitor that result from repeated charging and discharging cycles. These voltage oscillations serve as the detectable signal that indicates active mode, while their absence indicates sleep mode.
Data Source
AI summary
A clock detector is provided. The clock detector generally comprises a filter, a first branch, a second branch, a latch, and logic. The filter is adapted to receive a clock signal and is coupled to a low threshold inverter in the first branch and a high threshold inverter in the second branch. The latch is adapted to receive the clock signal and is coupled to the first branch, while the logic is coupled to the node between the first branch and the latch, an output of the latch, and the second branch so that it can output a clock detection signal.