Comparator Offset Calibration for High-Resolution Fast Input Sensing
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Solution Overview
Problem
Integrated circuit comparators face a trade-off between input resolution and response speed due to random transistor variations, which result in increased dc-input offsets, and larger transistors are needed to reduce offsets but increase power consumption and layout area.
Innovation Solution
Incorporating a pair of differential offset compensation transistors, proportionally smaller than the input transistors, and a control circuit to generate unequal dc offset voltages during calibration, adjusting these voltages until a dither is detected at the comparator output, to compensate for random transistor variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If smaller input transistors are used for higher response speed, then response speed is improved, but dc-input offset increases
Solution Approach 1:
The patent applies preliminary action by performing offset calibration before normal comparator operation. A calibration circuit generates compensating offset voltages that are stored in memory elements (such as capacitors or flip-flops) and then applied to the differential input transistors during normal operation. This pre-calibration approach allows the system to eliminate dc-input offsets without requiring larger transistors, thereby maintaining high response speed while improving measurement precision.
2Measurement precision
If larger transistors are used to reduce dc-input offsets, then measurement precision is improved, but power consumption and layout area increase
Solution Approach 1:
The patent uses preliminary calibration to generate and store compensating offset voltages in memory elements before normal operation. During normal comparator operation, these stored voltages are applied to cancel the effects of transistor variations. This approach eliminates the need to use larger transistors to reduce offsets, thereby maintaining low power consumption and small layout area while achieving high measurement precision.
3Measurement precision
If larger transistors are used to reduce dc-input offsets, then measurement precision is improved, but layout area increases
Solution Approach 1:
The patent implements preliminary offset calibration using a calibration circuit that generates compensating voltages and stores them in compact memory elements such as capacitors or flip-flops. During normal operation, these stored compensating voltages are applied to the differential input transistors to cancel offset errors. This approach achieves high measurement precision without requiring larger transistor layouts, thereby maintaining compact device area.
4Measurement precision
If offset compensation is implemented, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent performs offset calibration in advance and stores the compensating values in memory elements. During normal comparator operation, the stored compensating voltages are automatically applied without requiring complex real-time adjustment circuits. This preliminary calibration approach simplifies the main comparator circuit while still achieving high measurement precision, as the complex calibration function is separated into a dedicated pre-processing stage.
Data Source
AI summary
An integrated circuit comparator includes a pair of differential input transistors having gate terminals configured to receive a pair of differential input signals and a comparator output circuit electrically coupled to the pair of differential input transistors. A pair of differential offset compensation transistors are also provided. This pair of differential offset compensation transistors, which is electrically coupled to the pair of differential input transistors, has gate terminals that are configured to receive a pair of unequal dc offset voltages. The source and drain terminals of a first one of the pair of differential input transistors are electrically connected to corresponding source and drain terminals of a first one of the pair of differential offset compensation transistors and the source and drain terminals of a second one of the pair of differential input transistors are electrically connected to corresponding source and drain terminals of a second one of the pair of differential offset compensation transistors.