Asymmetric DFE Slicing for Transition-Bit Voltage Margin
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Solution Overview
Problem
High-speed digital communication systems face challenges in accurately interpreting signals due to jitter and inter-symbol interference, leading to bit errors, as existing equalization techniques are insufficient in providing sufficient margins for signal degradation.
Innovation Solution
A receiver circuit with a voltage measuring unit and comparator unit that adjusts an evaluation threshold voltage based on signal voltage differences, generating control signals to converge the threshold towards or away from the signal voltage, thereby improving voltage margins for transition bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If decision feedback equalization is used to compensate for ISI and jitter, then bit error reduction is achieved, but the receiver cannot provide sufficient voltage margins for accurate signal interpretation
Solution Approach 1:
The receiver dynamically adjusts the evaluation threshold voltage based on the detected logic value (0 or 1) of received signals. The threshold shifts between a first evaluation threshold and a second evaluation threshold, allowing the system to adapt to different signal conditions and provide sufficient voltage margins for accurate interpretation while maintaining bit error reduction through DFE compensation.
2Device complexity
If a fixed evaluation threshold is used for signal interpretation, then the receiver structure is simple, but voltage margins are insufficient for transition bits in high-speed communication
Solution Approach 1:
The receiver employs dynamic threshold adjustment where the evaluation threshold voltage changes based on the detected logic value. When logic 0 is detected, the threshold shifts to a first evaluation threshold; when logic 1 is detected, it shifts to a second evaluation threshold. This dynamic adaptation provides sufficient voltage margins for transition bits without requiring complex additional circuitry, maintaining relative structural simplicity while improving reliability.
Data Source
AI summary
An asymmetric DFE receiver circuit. The receiver circuit includes a voltage measuring unit configured to determine a signal voltage of a received signal, and a comparator unit configured to calculate a difference between the signal voltage and an evaluation threshold voltage and to compare the difference to the value of a midpoint voltage. The comparator unit is configured to generate a first control signal if the difference is greater than the midpoint voltage value or a second control signal if the signal voltage is less than the midpoint voltage value. The receiver includes an adjustment circuit configured to adjust the evaluation threshold voltage toward the signal voltage if the first control signal is generated and away from the signal voltage if the second control signal is generated. The rates of adjustment may vary depending upon whether the received signal is a transition bit or a non-transition bit.