Clock Frequency Discriminator With Edge Filtering for Duty Cycle Integrity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing frequency filtering systems face issues such as high speed clock signals leaking through during transitions, distortion of clock duty cycles due to RC filtering, and excessive power dissipation, particularly when high and low speed clocks share the same wire connection.
Innovation Solution
The solution involves filtering the rising and falling edges of clock signals using low pass filters to discriminate between high and low speed modes, regenerating the clock to match the input mode without allowing high speed signals to leak through, and eliminating the need for a free-running oscillator, thereby reducing power consumption and circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If RC filters are employed to filter clock signals, then frequency discrimination is achieved, but high speed clock signals leak through during transitions and duty cycles are distorted
Solution Approach 1:
The patent segments the clock signal filtering into separate rising edge filter and falling edge filter paths. Each edge type is filtered independently with optimized time constants, preventing the leakage and distortion problems of conventional single-path RC filtering while maintaining frequency discrimination accuracy.
Solution Approach 2:
The patent changes the filtering parameters by using different time constants for rising edge filtering versus falling edge filtering. This asymmetric parameter selection allows each edge to be optimized for its specific transition characteristics, eliminating the compromise required in conventional symmetric RC filtering.
2Duration of action of stationary object
If a free running oscillator is used to generate clock signals, then continuous clock operation is achieved, but power dissipation increases and circuit footprint expands
Solution Approach 1:
The patent eliminates the free-running oscillator and instead uses the incoming clock signal itself to drive the filtering and discrimination logic. The system serves itself by using the input signal as both the clock source and the reference for frequency detection, removing the need for separate oscillation generation and reducing power consumption.
Solution Approach 2:
The incoming clock signal performs multiple functions: it serves as the clock source for the system, the reference signal for frequency comparison, and the input to the filtering network. This multi-functionality eliminates the need for a dedicated free-running oscillator, reducing both power dissipation and circuit footprint.
3Quantity of substance
If high speed and low speed clocks share the same wire connection, then wire usage is optimized, but high speed signals interfere with low speed operations during transitions
Solution Approach 1:
The patent introduces separate rising edge filter and falling edge filter networks as intermediary elements between the shared clock line and the discrimination logic. These filters act as mediators that condition the high-speed transitions before they reach the low-speed logic, preventing interference while allowing both speeds to coexist on the same wire.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents high speed clock signals from interfering with low speed signals during transitions, maintains the original duty cycle, and reduces power consumption by eliminating the need for a separate oscillator, resulting in a more efficient and compact frequency filtering system.
Implementation Method 1
filtering the rising edge of the clock and the falling edge of the clock
Data Source
AI summary
A circuit is described that detects high and low frequencies and additional clock frequencies and outputs a signal that indicates a high, a low frequency or an additional mode. When in the low frequency low frequency mode signals are regenerated free of any high frequency signals from appearing on the filtered low frequency clock line. The rising and falling edges of the input clock are low pass filtered separately and then combined to generate a low frequency clock or the additional input clock and that retains the input clock pulse width and duty cycle.