LVDS Driver Slew Control for Symmetric Output Transitions
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Solution Overview
Problem
Low voltage differential signalling drivers face issues with asymmetric slew rates when operating at frequencies, particularly at 1.8V supply voltage, leading to signal integrity problems due to varying common mode voltage and increased current variation in current sources, which existing solutions like parallel current sources or feedback mechanisms fail to adequately address without increasing static current consumption or introducing jitter.
Innovation Solution
Incorporation of slew control circuitry that establishes a current discharge path during polarity transitions to balance the charging and discharging rates of output nodes, eliminating the need for parallel current sources and maintaining symmetric slew rates without increasing static current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the LVDS driver operates at 1.8V supply voltage, then power consumption is reduced, but asymmetric slew rate occurs leading to signal integrity problems
Solution Approach 1:
The patent intentionally introduces asymmetry through the slew control circuitry that provides different current paths for charging and discharging phases. During polarity transitions, the circuit establishes a current discharge path that balances the asymmetric slew rates caused by limited voltage headroom at 1.8V operation
Solution Approach 2:
The patent changes the electrical parameters dynamically by switching between different current source configurations. The slew control circuitry modifies the effective current magnitude and path based on the switching phase, adjusting parameters to maintain symmetric slew rates despite operating at reduced voltage
2Reliability
If parallel current sources are used to address asymmetric slew rate, then signal integrity is improved, but static current consumption increases
Solution Approach 1:
The patent employs periodic switching action where the slew control circuitry activates current discharge paths only during polarity transitions. This periodic intervention corrects asymmetric slew rates momentarily when needed, rather than maintaining continuous parallel current paths that would increase static consumption
Solution Approach 2:
The slew control circuitry anticipates polarity transitions and pre-establishes appropriate current discharge paths before the transition occurs. This preliminary action ensures symmetric slew rates are maintained without requiring continuous parallel current sources
3Reliability
If feedback mechanisms are used to correct asymmetric slew rate, then signal integrity is improved, but system complexity and jitter are introduced
Solution Approach 1:
The patent uses preliminary action by pre-configuring the slew control circuitry with delayed versions of control signals. The circuit anticipates polarity transitions and pre-establishes current discharge paths, eliminating the need for feedback mechanisms that would add complexity and potential jitter
Solution Approach 2:
The slew control circuitry acts as an intermediary between the differential input signal and the current sources. It processes the control signals through delay circuits and logic gates to generate appropriate switching signals, mediating the asymmetric slew rate issue without requiring complex feedback loops
Data Source
AI summary
A low voltage differential signalling driver is provided in which a first output node and a second output node provide a differential signal. First differential steering switch circuitry is switched in dependence on a differential input signal to selectively connect the first output node to a voltage supply via a current source, while second differential steering circuitry is switched in dependence on an inverse version of the differential input signal to connect the second output node to the voltage supply via the current source. Slew control circuitry is provided, configured to establish a current discharge path for the current source during the polarity transition of the differential input signal, thus maintaining a symmetric slew rate of the output signals at the first output node and second output node.