Fail-Safe IO Circuit for High-Impedance Standby Bus Isolation
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Solution Overview
Problem
Conventional fail-safe circuits in electronic systems with multiple subsystems connected via a common bus generate faulty signals and increase power consumption due to undesired current flow and noise when a subsystem is in standby mode, leading to reduced system reliability and increased power consumption.
Innovation Solution
A semiconductor integrated circuit device with a fail-safe IO circuit that maintains IO ports at high impedance during standby mode, using a control signal to manage IO power and include noise-blocking buffers with RC filters and Schmitt-trigger inverters to prevent erroneous signal transmission, and an NMOS transistor for IO power clamping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a subsystem is set to standby mode with turned off core and IO powers, then power consumption is reduced, but undesired current flow and noise occur through the common bus
Solution Approach 1:
The fail-safe IO circuit applies preliminary anti-action by proactively maintaining IO ports in high-impedance state before actual signal transmission occurs. When a subsystem enters standby mode, the control signal immediately configures the IO circuit to present high impedance to the common bus, preventing undesired current flow and noise from affecting the standby subsystem. This preemptive configuration eliminates the harmful effects before they can manifest.
Solution Approach 2:
The fail-safe IO circuit acts as an intermediary between the IO ports and the common bus. It introduces a control mechanism that mediates the interaction between active and standby subsystems by dynamically adjusting the impedance state of IO ports based on operational mode. This intermediary function isolates standby subsystems from harmful electrical interactions on the common bus while maintaining system connectivity.
2Device complexity
If IO ports are not maintained at high impedance in standby mode, then signal transmission is simpler, but false signals and noise are generated on the common bus
Solution Approach 1:
The fail-safe IO circuit implements dynamics by making the impedance state of IO ports changeable based on operational requirements. The circuit transitions between low-impedance state during active operation and high-impedance state during standby mode, controlled by the fail-safe control signal. This dynamic adaptation allows the IO circuit to optimize both signal transmission quality and power consumption according to the subsystem's operational state.
Solution Approach 2:
The invention applies parameter changes by modifying the electrical impedance parameter of IO ports based on the operational mode. During standby, the impedance is changed to a high value to prevent current flow, while during active operation, the impedance returns to a low value for proper signal transmission. This parameter transformation is controlled by the fail-safe control signal and achieved through the gate circuit configuration.
3Reliability
If noise-blocking buffers with RC filters and Schmitt-trigger inverters are added, then signal integrity is improved, but device complexity increases
Solution Approach 1:
The noise-blocking buffers with RC filters and Schmitt-trigger inverters apply preliminary action by preprocessing control signals before they reach the gate circuit. The RC filter removes high-frequency noise, and the Schmitt-trigger inverter provides hysteresis to clean up signal transitions. This preliminary signal conditioning ensures that only clean, valid control signals activate the fail-safe mode, preventing false triggering while maintaining system reliability.
Data Source
AI summary
A semiconductor IC device includes at least one IO port, a core logic, and at least one fail-safe IO circuit, the fail-safe IO circuit being coupled between the core logic and the IO port, wherein the fail-safe IO circuit is configured to receive a predetermined control signal and to maintain the IO port at a predetermined impedance with respect to the predetermined control signal.